THS1060_05 Datasheet, PDF (3/22 Pages) Texas Instruments – 10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS

THS1060
10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS212A – MARCH 2000 – REVISED MARCH 2001
Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
AVDD
2, 5, 12
43, 45, 47
I Analog power supply
AVSS
1, 11, 13, I Analog ground return for internal analog circuitry
41, 42, 44,
46
CLK+
15
I Clock input
CLK–
16
I Complementary clock input
D9–D0
25–34
O Digital data output bits; LSB= D0, MSB = D9 (2s complement output format)
DRVDD
DRVSS
DVDD
DVSS
VBG
VCM
VIN+
VIN_–
VREFIN _–
VREFIN+
VREFOUT+
VREFOUT _–
24, 37, 38
23, 39, 40
17, 20, 22
18, 19, 21
10
48
3
4
7
8
9
6
I Digital output driver supply
I Digital output driver ground return
I Positive digital supply
I Digital ground return
O Band gap reference. Bypass to ground with a 1-µF and a 0.01-µF chip capacitor.
O Common mode voltage output. Bypass to ground with a 0.1-µF and a 0.01-µF chip device capacitor.
I Analog signal input
I Complementary analog signal input
I External reference input low
I External reference input high
O Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.
O Internal reference output. Compensate with a 1-µF and a 0.01-µF chip capacitor.
detailed description
The THS1060 uses a differential pipeline architecture and assures no missing codes over the full operating
temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible
bandwidth. The differential analog inputs are terminated with a 900 Ω resistor. The inputs are then fed to a unity
gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor op-amp based
circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional block diagram.
The digital output of the 10 stages and the last 1 bit flash are sent to a digital correction logic block which then
outputs the final 10 bits.
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