TCM320AC46 Datasheet, PDF (3/19 Pages) Texas Instruments – GEBERAL-PURPOSE AUDIO INTERFACE FOR DSP

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PIN
NAME
NO.
CLK
11
DCLKR
7
DIN
8
DOUT
13
EARA
2
EARB
3
EARGS
4
EARMUTE
10
FSR
9
FSX
12
GND
16
LINSEL
15
MICBIAS
20
MICGS
19
MICIN
18
MICMUTE
6
PDN
1
TSX/DCLKX 14
VCC
5
VMID
17
TCM320AC46
GENERALĆPURPOSE AUDIO INTERFACE FOR DSP
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SLWS001 − D4091, JUNE 1993
Terminal Functions
I/O
DESCRIPTION
I In the fixed-data-rate mode, CLK is the master clock input as well as the transmit and receive data clock input.
In the variable-data-rate mode, CLK serves only as the master clock input.
I Selects fixed- or variable-data-rate operation. When DCLKR is connected to VCC, the device operates in the
fixed-data-rate mode. When DCLKR is not connected to VCC, the device operates in the variable-data-rate mode
and DCLKR becomes the receive data clock.
I Receive data input. Input data is clocked in on consecutive negative transitions of the receive data clock, which
is CLK for a fixed data rate and DCLKR for a variable data rate.
O Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit data clock,
which is CLK for a fixed data rate and DCLKX for a variable data rate.
O Earphone output. EARA forms a differential drive when used with the EARB signal.
O Earphone output. EARB forms a differential drive when used with the EARA signal.
I Earphone gain set input of feedback signal for the earphone output. The ratio of an external potential divider
network connected across EARA and EARB adjusts the power amplifier gain. Maximum gain occurs when
EARGS is connected to EARB, and minimum gain occurs when EARGS is connected to EARA. Earphone
frequency response correction is performed using an external RC filter.
I Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no audio is
sent to the earphone.
I Frame synchronization clock input for receive channel. In the variable-data-rate mode, FSR must remain high
for the duration of the time slot. The receive channel enters the standby state when FSR is TTL low for five frames
or longer. The device enters a production test-mode condition when either FSR or FSX is held high for five frames
or longer.
I Frame synchronization clock input for transmit channel. FSX operates independently of, but in an analogous
manner to, FSR. The transmit channel enters the standby state when FSX is low for five frames or longer. The
device enters a production test-mode condition when either FSX or FSR is held high for five frames or longer.
Ground return for all internal analog and digital circuits
I Linear selection input. When low, LINSEL selects linear coding/decoding. When high, LINSEL selects
companded coding/decoding. The companded mode is µ-law.
O Bias voltage equal to VMID for the electret microphone
O Output of the internal microphone amplifier. MICGS used as the feedback to set the microphone amplifier gain.
If sidetone is required, it is accomplished by connecting a series network between MICGS and EARGS.
I Electret microphone input to the internal microphone amplifier
I Microphone input mute control signal. When MICMUTE is active (low), the input amplifier is disabled, the
microphone current is switched off, and zero code is transmitted.
I Power-down input. When low, the device powers down to reduce power consumption.
I/O Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the fixed-data-rate
mode, this is an open-drain output that pulls to ground and is used as an enable signal for a 3-state buffer. In
the variable-data-rate mode, DCLKX becomes the transmit data clock input.
5-V supply voltage for all internal analog and digital circuits
O VCC /2 bias voltage reference. An external, low-leakage, high-frequency 1-µF capacitor should be connected
to VMID for filtering.
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