TCM320AC46 Datasheet, PDF (16/19 Pages) Texas Instruments – GEBERAL-PURPOSE AUDIO INTERFACE FOR DSP

TCM320AC46
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GENERALĆPURPOSE AUDIO INTERFACE FOR DSP
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SLWS001 − D4091, JUNE 1993
PARAMETER MEASUREMENT INFORMATION
DCLKR
FSR
0
1
80%
20%
Receive Time Slot
2
3
4
80%
80%
N−2
20%
tsu(FSR)
tc(DCLKR)
See Note A
th(DIN)
N−1
N
N+1
80%
80%
20%
th(FSR)
See Note B
20%
DIN N −1
N
1
2
3
4
N−2
N−1
N
1
See Note C
tsu(DIN)
NOTES: A. This window is allowed for FSR high (tsu(FSR) max determined by data collision considerations).
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.
Figure 4. Variable-Data-Rate, Receive Side Timing Diagram
DCLKX
Transmit Time Slot
0
1
2
3
4
80%
20%
80%
80%
80%
N−2
N−1
N
20%
N+1
80%
tsu(FSX)
tc(DCLKR)
th(FSX)
FSX
80%
tpd7
80%
See Note A
See Note B
tpd6
tpd8
DOUT
See Note C
1
2
3
4
N−2
N−1 N
NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low without data repetition.
C. Transitions are measured at 50%.
Figure 5. Variable-Data-Rate, Transmit Side Timing Diagram
APPLICATION INFORMATION
output gain set design considerations (see Figure 6)
EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are:
V_{O +} at EARA
V_{O −} at EARB
V_OD = V_{O +} − V_{O −} (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.
A value greater than 10 kΩ and less than 100 kΩ for R1 + R2 is recommended because of the following:
The parallel combination R1 + R2 and R_L sets the total loading. The total capacitance at EARGS and the
parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
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