TCM320AC46 Datasheet, PDF (17/19 Pages) Texas Instruments – GEBERAL-PURPOSE AUDIO INTERFACE FOR DSP

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TCM320AC46
GENERALĆPURPOSE AUDIO INTERFACE FOR DSP
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SLWS001 − D4091, JUNE 1993
APPLICATION INFORMATION
V_A represents the maximum available digital mW output response (V_A = 1.06 Vrms).
V_OD = A × V_A
1 + (R1/R2)
where A = _{4 + (R1/R2)}
VO+
VO _−
RL VO
2
EARA
R1
4
EARGS DIN
R2
3
EARB
Digital mW Sequence
Per CCITT G.712
Figure 6. Gain-Setting Configuration
higher clock frequencies and sample rates
The TCM320AC46 is designed to work with sample rates up to 24 kHz where the frequency of the frame sync
determines the sampling frequency. However, there is a fundamental requirement to maintain the ratio of master
clock frequency, f_CLK, to frame sync frequency, f_FSR/f_FSX. This ratio for the device is 2.048 MHz/8 kHz or 256
master clocks per frame sync. For example, to operate the TCM320AC46 at a sampling rate of f_FSR and f_FSX
equal to 16 kHz, f_CLK must be 256 times 16 kHz, or 4.096 MHz. If the TCM320AC46 is operated above an 8-kHz
sample rate, however, it is expected that the performance will be degraded.
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