LMC6024 Datasheet, PDF (3/22 Pages) National Semiconductor (TI) – Low Power CMOS Quad Operational Amplifier

LMC6024
www.ti.com
SNOS621D – AUGUST 2000 – REVISED MARCH 2013
DC Electrical Characteristics
The following specifications apply for V⁺ = 5V, V^− = 0V, V_CM = 1.5V, V_O = 2.5V, and R_L = 1M unless otherwise noted.
Boldface limits apply at the temperature extremes; all other limits T_J = 25°C.
Parameter
Test Conditions
Typical ⁽¹⁾
LMC6024I
Limit ⁽²⁾
Units
V_OS
Input Offset Voltage
1
9
mV
11
Max
ΔV_OS/ΔT
Input Offset Voltage Average
Drift
2.5
μV/°C
I_B
Input Bias Current
0.04
pA
200
Max
I_OS
Input Offset Current
0.01
pA
100
Max
R_IN
CMRR
+PSRR
Input Resistance
Common Mode Rejection
Ratio
Positive Power Supply
Rejection Ratio
0V ≤ V_CM ≤ 12V
V⁺ = 15V
5V ≤ V⁺ ≤ 15V
>1
TeraΩ
83
63
dB
61
Min
83
63
dB
61
Min
−PSRR
V_CM
Negative Power Supply
Rejection Ratio
Input Common-Mode Voltage
Range
0V ≤ V^− ≤ −10V
V⁺ = 5V and 15V
For CMRR ≥ 50 DB
A_V
Large Signal Voltage Gain
R_L = 100 kΩ⁽³⁾
Sourcing
94
−0.4
V⁺ − 1.9
1000
74
73
−0.1
0
V⁺ − 2.3
V⁺ − 2.5
200
100
dB
Min
V
Max
V
Min
V/mV
Min
R_L = 5 kΩ ⁽³⁾
Sinking
Sourcing
500
1000
90
V/mV
40
Min
100
V/mV
75
Min
Sinking
V_O
Output Voltage Swing
V⁺ = 5V
R_L = 100 kΩ to 2.5V
250
4.987
50
V/mV
20
Min
4.40
V
4.43
Min
V⁺ = 5V
R_L = 5 kΩ to 2.5V
0.004
4.940
0.06
V
0.09
Max
4.20
V
4.00
Min
V⁺ = 15V
R_L = 100 kΩ to 7.5V
0.040
0.25
V
0.35
Max
14.970
14.00
V
13.90
Min
V⁺ = 15V
R_L = 5 kΩ to 7.5V
0.007
0.06
V
0.09
Max
14.840
13.70
V
13.50
Min
0.110
0.32
V
0.40
Max
(1) Typical values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or correlation.
(3) V⁺ = 15V, V_CM = 7.5V, and R_L connected to 7.5V. For Sourcing tests, 7.5V ≤ V_O ≤ 11.5V. For Sinking tests, 2.5V ≤ V_O ≤ 7.5V.
Copyright © 2000–2013, Texas Instruments Incorporated
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