DS90C402_13 Datasheet, PDF (3/14 Pages) Texas Instruments – Dual Low Voltage Differential Signaling (LVDS) Receiver

DS90C402
www.ti.com
SNLS001C – JUNE 1998 – REVISED APRIL 2013
Switching Characteristics
V_CC = +5.0V ± 10%, T_A = −40°C to +85°C^{(1)(2)(3)(4)(5)}
Symbol
Parameter
Conditions
Min Typ Max Units
t_PHLD
t_PLHD
t_SKD
t_SK1
t_SK2
t_TLH
t_THL
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Skew |t_PHLD − t_PLHD|
Channel-to-Channel Skew⁽³⁾
Chip to Chip Skew⁽⁴⁾
Rise Time
Fall Time
C_L = 5 pF,
V_ID = 200 mV
(Figure 1 and Figure 2)
1.0 3.40 6.0 ns
1.0 3.48 6.0 ns
0 0.08 1.2 ns
0
0.6 1.5 ns
5.0 ns
0.5 2.5 ns
0.5 2.5 ns
(1) All typicals are given for: V_CC = +5.0V, T_A = +25°C.
(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, t_r and t_f (0%–100%) ≤ 1 ns for R_IN.
(3) Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same
chip with an event on the inputs.
(4) Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
(5) C_L includes probe and jig capacitance.
Parameter Measurement Information
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
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