CDC586_08 Datasheet, PDF (3/14 Pages) Texas Instruments – 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER

CDC586
www.ti.com
SCAS336E – FEBRUARY 1993 – REVISED APRIL 2004
Output Configuration A
Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2x outputs operate at half the CLKIN frequency, while outputs configured as 1x outputs operate
at the same frequency as CLKIN.
Table 1. Output Configuration A⁽¹⁾
INPUTS
SEL1
SEL0
L
L
L
H
H
L
H
H
OUTPUTS
1/2x
FREQUENCY
1x
FREQUENCY
None
All
1Yn
2Yn, 3Yn, 4Yn
1Yn, 2Yn
3Yn, 4Yn
1Yn, 2Yn, 3Yn
4Yn
(1) n = 1, 2, 3
Output Configuration B
Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at
double the frequency of CLKIN.
Table 2. Output Configuration B⁽¹⁾
INPUTS
SEL1
SEL0
L
L
L
H
H
L
H
H
OUTPUTS
1x
FREQUENCY
2x
FREQUENCY
All
None
1Yn
2Yn, 3Yn, 4Yn
1Yn, 2Yn
3Yn, 4Yn
1Yn, 2Yn, 3Yn
4Yn
(1) n = 1, 2, 3
3