BQ3285E_15 Datasheet, PDF (3/36 Pages) Texas Instruments – Real-Time Clock (RTC)

bq3285E/L
DS
R/W
CS
INT
SQW
Data strobe input
When MOT = VCC, DS controls data trans-
fer during a bq3285E/L bus cycle. During a
read cycle, the bq3285E/L drives the bus af-
ter the rising edge on DS. During a write
cycle, the falling edge on DS is used to latch
write data into the chip.
When MOT = VSS, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.
Read/write input
When MOT = VCC, the level on R/W identi-
fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.
When MOT = VSS, R/W is provided a sig-
nal similar to WR, MEMW, or I/OW in an
Intel-based system. The rising edge on
R/W latches data into the bq3285E/L.
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq3285E/L.
Interrupt request output
INT is an open-drain output. This allows
alarm INT to be valid in battery-backup
mode. To use this feature, INT must be con-
nected to a power supply other than VCC.
INT is asserted low when any event flag is
set and the corresponding event enable bit
is also set. INT becomes high-impedance
whenever register C is read (see the Con-
trol/Status Registers section).
Square-wave output
SQW may output a programmable fre-
quency square-wave signal during normal
(VCC valid) system operation. Any one of
the 13 specific frequencies may be selected
through register A. This pin is held low
when the square-wave enable bit (SQWE)
in register B is 0 (see the Control/Status
Registers section).
A 32.768kHz output is enabled by setting
the SQWE bit in register B to 1 and the
32KE bit in register C to 1 after setting
OSC2–OSC0 in register A to 011 (binary).
EXTRAM Extended RAM enable
Enables 128 bytes of additional nonvolatile
SRAM. It is connected internally to a 30K
Ω pull-down resistor. To access the RTC
registers, EXTRAM must be low.
RCL
RAM clear input
A low level on the RCL pin causes the con-
tents of each of the 242 storage bytes to be
set to FF(hex). The contents of the clock
and control registers are unaffected. This
pin should be used as a user-interface input
(pushbutton to ground) and not connected
to the output of any active component. RCL
input is only recognized when held low for
at least 125ms in the presence of VCC. Us-
ing RAM clear does not affect the battery
load. This pin is connected internally to a
30KΩ pull-up resistor.
BC
3V backup cell input
BC should be connected to a 3V backup cell
for RTC operation and storage register non-
volatility in the absence of system power.
When VCC slews down past VBC (3V typical),
the integral control circuitry switches the
power source to BC. When VCC returns
above VBC, the power source is switched to
VCC.
Upon power-up, a voltage within the VBC
range must be present on the BC pin for
the oscillator to start up.
RST
Reset input
The bq3285E/L is reset when RST is pulled
low. When reset, INT becomes high imped-
ance, and the bq3285E/L is not accessible.
Table 4 in the Control/Status Registers sec-
tion lists the register bits that are cleared
by a reset.
Reset may be disabled by connecting RST
to VCC. This allows the control bits to re-
tain their states through power-
down/power-up cycles.
X1–X2
Crystal inputs
The X1–X2 inputs are provided for an exter-
nal 32.768kHz quartz crystal, Daiwa DT-26
or equivalent, with 6pF load capacitance. A
trimming capacitor may be necessary for ex-
tremely precise time-base generation.
In the absence of a crystal, a 32.768kHz
waveform can be fed into the X1 input.
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