BQ3285E_15 Datasheet, PDF (10/36 Pages) Texas Instruments – Real-Time Clock (RTC)

bq3285E/L
UTI - Update Transfer Inhibit
7
6
5
4
3
UTI -
-
-
-
2
1
0
-
-
-
This bit inhibits the transfer of RTC bytes to the user
buffer:
1 = Inhibits transfer and clears UIE
0 = Allows transfer
Register C
Register C is the read-only event status register.
Register C Bits
7
6
5
4
3
2
1
0
INTF PF AF UF
0 32KE 0
0
Bits 0, 1, 3 - Unused Bits
These bits are always set to 0.
7
6
5
4
3
2
1
0
-
-
-
-
0
-
0
0
32KE - 32kHz Enable Output
This bit may be set to a 1 only when the OSC2–OSC0
bits in register A are set to 011. Setting OSC2–OSC0 to
7
6
5
4
-
-
-
-
3
2
1
0
- 32KE -
-
anything other than 011 clears this bit. If SQWE in reg-
ister B and 32KE are set, a 32.768kHz waveform is out-
put on the square wave pin.
UF - Update Event Flag
This bit is set to a 1 at the end of the update cycle.
7
6
5
4
3
-
-
- UF -
2
1
0
-
-
-
Reading register C clears this bit.
PF - Periodic Event Flag
This bit is set to a 1 every tPI time, where tPI is the time
period selected by the settings of RS0–RS3 in register A.
Reading register C clears this bit.
7
6
5
4
3
2
1
0
- PF -
-
-
-
-
-
INTF - Interrupt Request Flag
This flag is set to a 1 when any of the following is true:
AIE = 1 and AF = 1
PIE = 1 and PF = 1
7
6
5
4
3
2
1
0
INTF -
-
-
-
-
-
-
UIE = 1 and UF = 1
Reading register C clears this bit.
Register D
Register D is the read-only data integrity status register.
Bits 0–6 - Unused Bits
These bits are always set to 0.
VRT - Valid RAM and Time
Register D Bits
7
6
5
4
3
2
1
0
VRT 0
0
0
0
0
0
0
1 = Valid backup energy source
0 = Backup energy source is depleted
7
6
5
4
3
2
1
0
-
0
0
0
0
0
0
0
When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.
7
6
5
4
3
2
1
0
VRT -
-
-
-
-
-
-
AF - Alarm Event Flag
This bit is set to a 1 when an alarm event occurs. Read-
ing register C clears this bit.
7
6
5
4
3
2
1
0
-
- AF -
-
-
-
-
10