ADS7870_14 Datasheet, PDF (3/45 Pages) Texas Instruments – 12-BIT, 52-kSPS, DATA ACQUISITION SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER, MUX, PGA, AND REFERENCE

ADS7870
www.ti.com
SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
ELECTRICAL CHARACTERISTICS
For the Total System ^(1), −40°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless
otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Input
Input voltage (LNx inputs)
Input capacitance ⁽²⁾
Linear operation
−0.2
VDD + 0.2
V
4 to 9.7
pF
Input impedance ⁽²⁾
Common mode
Differential
Channel-to-channel crosstalk
Maximum leakage current
VI = 2 VPP, 60 Hz ⁽³⁾
6
MΩ
7
100
dB
100
pA
Static Accuracy
Resolution
12
Bits
No missing codes
G = 1 to 20 V/V
12
Bits
Integral linearity
G = 1 to 20 V/V
−2.5
±2
2.5
LSB
Differential linearity
G = 1 to 20 V/V
±0.5
LSB
Offset error
G = 1 to 20 V/V
−6
±1
6
LSB
Full-scale gain error
Ratiometric configuration or
external reference ⁽⁴⁾
Internal reference
G = 1 to 10 V/V
G = 16 and 20 V/V
G = 1 to 10 V/V
G = 16 and 20 V/V
−0.2
−0.25
−0.35
−0.4
0.2 %FSR
0.25 %FSR
0.35 %FSR
0.4 %FSR
DC common-mode rejection ratio, RTI
VI = −0.2 V to 5.2 V,
G = 20 V/V
92
dB
Power supply rejection ratio, RTI
Dynamic Characteristics
VDD = 5 V ±10%, G = 20 V/V
86
dB
Throughput rate
Continuous mode
Address mode
One channel
Different channels
External clock, CCLK ⁽⁵⁾
0.1
52
ksample/s
52
20
MHz
Internal oscillator frequency
2.5
MHz
Serial interface clock, SCLK
20
MHz
Data setup time
10
ns
Data hold time
10
ns
Digital Inputs
Logic levels
Low-level input voltage, VIL
High-level input voltage, VIH
Low-level input current, IIL
High-level input current, IIH
VDD ≤ 3.6 V
VDD > 3.6 V
0.8
V
2
V
3
V
1
µA
1
(1) _{The specifications for the total system are overall analog input to digital output specifications. The specifications for internal functions indicate}
the performance of the individual functions in the ADS7870.
(2) _{The ADS7870 uses switched capacitor techniques for the programmable gain amplifier and A/D converter. A characteristic of such circuits is that}
the input capacitance at any selected LNx pin changes during the conversion cycle.
(3) _{One channel on with its inputs grounded. All other channels off with sinewave voltage applied to their inputs.}
(4) _{Ratiometric configuration exists when the input source is configured such that changes in the reference cause corresponding changes in the input}
voltage. The same accuracy applies when a perfect external reference is used.
(5) _{The CCLK is divided by the DF value specified by the contents of register 3, A/D Control register, bits D0 and D1 to produce DCLK. The maximum}
value of DCLK is 2.5 MHz.
3