ADS7870_14 Datasheet, PDF (16/45 Pages) Texas Instruments – 12-BIT, 52-kSPS, DATA ACQUISITION SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER, MUX, PGA, AND REFERENCE

ADS7870
SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
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Note that the seven lower bits of this byte are written to register 4, the Gain/Mux register.
All other controllable ADS7870 parameters are values previously stored in their respective registers. These
values are either the power-up default values (0) or values that were previously written to one of the control
registers in a register mode operation. No additional data is required for a direct mode instruction.
Register Mode
In register mode (Bit D7 of the Instruction Byte is 0) a read or write instruction to one of the ADS7870’s registers
is initiated. All of the user determinable functions and features of the ADS7870 can be controlled by writing
information to these registers (see Figure 15). Conversion results can be read from the A/D Output registers.
REGISTER ADDRESS
A4 A3 A2 A1 A0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
ADDR READ/ D7
NO. WRITE (MSB)
0
Read ADC3
D6
ADC2
REGISTER CONTENT
D5
D4
D3
D2
ADC1 ADC0
0
0
1
Read ADC11 ADC10 ADC9 ADC8 ADC7 ADC6
2
Read
0
0
VLD5 VLD4 VLD3 VLD2
3
R/W
0
0
BIN
0
RMB1 RBM0
4
R/W
CNV/
BSY
G2
G1
G0
M3
M2
5
R/W
CNV/
BSY
0
0
0
IO3
IO2
6
R/W
0
0
0
0
OE3
OE2
7
R/W
0
0
OSCR OSCE REFE BUFE
24
R/W LSB 2W/3W 8051
0
31
Read
0
0
0
0
0
8501
0
0
D1
0
ADC5
VLD1
CFD1
M1
IO1
OE1
R2V
2W/3W
0
D0
OVR
ADC4
VLD0
CFD0
REGISTER NAME
A/D Output Data,
LS Byte
A/D Output Data,
MS Byte
PGA Valid Register
A/D Control Register
M0 Gain/Mux Register
IO0
OE0
RBG
LSB
1
Digital I/O State
Register
Digital I/O Control
Register
Ref/Oscillator
Control Register
Serial Interface
Control Register
ID Register
Figure 15. Register Address Map
The instruction byte (see Figure 14) contains the address of the register for the next read/write operation,
determines whether the serial communication is to be done in 8-bit or 16-bit word length, and determines
whether the next operation is read-from or written-to the addressed register.
The structure of the instruction byte for register mode is shown in Figure 14.
D D7: This bit is set to 0 for register mode operation.
D D6 (R/W): Bit 6 of the instruction byte determines whether a read or write operation is performed, 1 for
a read or 0 for a write.
D D5 (16/8): This bit determines the word length of the read or write operation that follows, 1 for sixteen bits
(two eight-bit bytes) or 0 for eight bits.
D D4 through D0 (A4 − A0): These bits determine the address of the register that is to be read from or written
to. Register address coding and other information are tabulated in Figure 15.
For sixteen-bit operations, the first eight bits is written-to/read-from the address encoded by the instruction byte,
bits A4 through A0 (register address). The address of the next eight bits depends upon whether the register
address for the first byte is odd or even. If it is even, then the address for the second byte is the register address
+ 1. If the register address is odd, then the address for the second byte is the register address – 1.
This arrangement allows transfer of conversion results from the two A/D Output Data registers either MS byte
first or LS byte first (refer to the section Serial Interface Control Register).
Register Summary
A summary of information about the addressable registers is shown in Figure 15. Their descriptions follow, and
more detailed information is provided later in the section Internal User-Accessible Registers.
Registers 0 and 1, the A/D Output Data registers, contain the least significant and most significant bits of the
A/D conversion result (ADC0 through ADC13). Register 0 also has three fixed zeros (D3, D2, and D1), and a
bit to indicate if the internal voltage limits of the PGA have been over ranged (OVR). This is a read only register.
Write an 8-bit word to register 0 and the ADS7870 resets.
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