ADS7870_14 Datasheet, PDF (23/45 Pages) Texas Instruments – 12-BIT, 52-kSPS, DATA ACQUISITION SYSTEM WITH ANALOG-TO-DIGITAL CONVERTER, MUX, PGA, AND REFERENCE

ADS7870
www.ti.com
SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
A/D Control Register
The A/D Control register (ADDR = 3) configures the CCLK divider and read back mode option as shown in
Figure 24.
ADDR
D7 (MSB)
D6
3
0
0
ADC CONTROL REGISTER
D5
D4
D3
BIN
0
RBM1
D2
RBM0
D1
CFD1
D0
CFD0
ADDR = 3
BIT
D7−D6
D5
D4
D3−D2
SYMBOL
—
BIN
—
RBM1−RBM0
NAME
—
Output Data
Format
—
Automatic Read
Back Mode
D1−D0 CFD1−CFD0 CCLK Divide
Bold items are power-up default conditions.
VALUE
FUNCTION
0 These bits are reserved and must always be written 0.
0 Mode 0 − Twos complement output data format
1 Mode 1 − Binary output data format
0 This is a reserved bit and must always be written 0.
00 Mode 0 − Read instruction required to access ADC conversion result.
01 Mode 1 − Most significant byte returned first
10 Mode 2 − Least significant byte returned first
11 Mode 3 − Only most significant byte returned
00 Division factor for CCLK = 1 (DCLK = CCLK)
01 Division factor for CCLK = 2 (DCLK = CCLK/2)
10 Division factor for CCLK = 4 (DCLK = CCLK/4)
11 Division factor for CCLK = 8 (DCLK = CCLK/8)
Figure 24. ADC Control Register (ADDR = 3)
Read Back Modes
RBM1 and RBM0 determine which of four possible modes is used to read the A/D conversion result from the
A/D Output registers.
D Mode 0 (default mode) requires a separate read instruction to be performed in order to read the output
of the A/D Output registers
D Mode 1, 2, and 3: Provide for different types of automatic read-back options of the conversion results from
the A/D Output registers without having to use separate read instructions:
Mode 1: Provides data MS byte first
Mode 2: Provides data LS byte first
Mode 3: Output only the MS byte
For more information refer to the Read Back Mode section.
Clock Divider
CFD1 and CFD0 set the CCLK divisor constant which determines the DCLK applied to the A/D, PGA, and
reference. The A/D and PGA operate with a maximum clock of 2.5 MHz. In situations where an external clock
is used to pace the conversion process it may be desirable to reduce the external clock frequency before it is
actually applied to the PGA and A/D. The signal that is actually applied to the A/D and PGA is called DCLK,
where DCLK = CCLK/DF (DF is the division factor determined by the CFD1 and CFD0 bits). For example, if
the external clock applied to CCLK is 10 MHz and DF = 4 (CFD1 = 1, CFD0 = 0), DCLK equals 2.5 MHz.
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