OPA196 Datasheet, PDF (29/47 Pages) Texas Instruments – 36-V, Low-Power, Low Offset Voltage, Rail-to-Rail Operational Amplifier

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OPA196, OPA2196, OPA4196
SBOS869 – JULY 2017
Typical Applications (continued)
8.2.2 16-Bit Precision Multiplexed Data-Acquisition System
Figure 49 shows a 16-bit, differential, 4-channel, multiplexed, data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR), analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front-end, and a 4-channel differential multiplexer (mux). This
application example shows the process for optimizing the precision, high-voltage, front-end drive circuit using the
OPA196 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864. The full TI
Precision Design can be found in TIDU181.
1
Very Low Output
Impedance
Input-Filter Bandwidth
2
High-Impedance Inputs
No Differential Input
Clamps
Fast Settling-Time
Requirements
3
4
Attenuate High-Voltage Input
Signal
Fast-Settling Time
Requirements
Stability of the Input Driver
Attenuate ADC Kickback
Noise
VREF Output: Value and
Accuracy
Low Temp and Long-Term
Drift
±20-V,
10-kHz
Sine
Wave
±20-V,
10-kHz
Sine
Wave
+
OPA196
+
OPA196
CH0+
CH0-
4:2
Mux
+
OPA196
+
OPA196
CH3+
CH3-
n
High-Voltage Multiplexed Input
OPA196
+
Gain
Network
Gain
Network
Voltage
Reference
RC
Buffer
Filter
Reference
Driver
RC
Filter
+
OPA196
Gain
Network
OPA140
+
High-Voltage Level
Translation
VCM
REF3240
Voltage
Divider
OPA350
VCM Generation Circuit
5 Fast logic transition
Antialiasing
Filter
VINP
REFP
SAR
ADC
VINM
CONV
16 Bits
400 kSPS
Counter
n
Shmidtt
Trigger
Delay
Digital Counter For
Multiplexer
Figure 49. OPA196 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage
Inputs With Lowest Distortion
8.2.2.1 Design Requirements
The primary objective is to design a ±20-V, differential, 4-channel, multiplexed, data acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure sine-wave
input. The design requirements for this block design are:
• System supply voltage: ±15 V
• ADC supply voltage: 3.3 V
• ADC sampling rate: 400 kSPS
• ADC reference voltage (REFP): 4.096 V
• System input signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency
(f_IN) of 10 kHz are applied to each differential input of the mux.
8.2.2.2 Detailed Design Procedure
The purpose of this application example is to design an optimal, high-voltage, multiplexed, data-acquisition
system for highest system linearity and fast settling. The overall system block diagram is shown in Figure 49.
The circuit is a multichannel, data-acquisition, signal chain consisting of an input low-pass filter, multiplexer
(mux), mux output buffer, attenuating SAR ADC driver, digital counter for the mux, and the reference driver. The
architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two
primary design considerations to maximize the performance of a precision, multiplexed, data-acquisition system
are the mux input analog front-end and the high-voltage, level translation, SAR ADC driver design. However,
carefully design each analog circuit block based on the ADC performance specifications in order to achieve the
fastest settling at 16-bit resolution and lowest distortion system. Figure 49 includes the most important
specifications for each individual analog block.
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