LMX2486_16 Datasheet, PDF (29/47 Pages) Texas Instruments – Low-Power Dual PLLatinum Frequency Synthesizers

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LMX2486
SNAS324B – JANUARY 2006 – REVISED JANUARY 2016
8.6.3 R2 Register
Table 20. R2 Register
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[19:0]
C3 C2 C1 C0
R2
IF_PD
IF_N[18:0]
0101
8.6.3.1 IF_N[18:0] -- IF N Divider Value
N VALUE
≤23
24-55
56
57
...
262143
Table 21. IF_N Counter Programming With the 8/9 Prescaler (IF_P=0)
IF_N[18:0]
IF_B
IF_A
N values less than or equal to 23 are prohibited because IF_B ≥ 3 is required.
Legal divide ratios in this range are:
24-27, 32-36, 40-45, 48-54
0000000000001110000
0000000000001110001
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1111111111111110111
N VALUE
≤47
48-239
240
241
...
524287
Table 22. Operation With the 16/17 Prescaler (IF_P=1)
IF_B
IF_A
N values less than or equal to 47 are prohibited because IF_B ≥ 3 is required.
Legal divide ratios in this range are:
48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238
0000000000011110000
0000000000011110001
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1111111111111111111
8.6.3.2 IF_PD -- IF Power Down Bit
When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the
output of the IF PLL charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written
to, the IF_PD will be reset to 0 and the IF PLL will be powered up. If the CE pin is held low, the IF PLL will be
powered down, overriding the IF_PD bit.
8.6.4 R3 Register
Table 23. R3 Register
REGISTER 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[19:0]
C3 C2 C1 C0
R3
ACCESS[3:0]
RF_CPG[3:0]
IF_R[11:0]
0111
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