LMX2486_16 Datasheet, PDF (17/47 Pages) Texas Instruments – Low-Power Dual PLLatinum Frequency Synthesizers

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LMX2486
SNAS324B – JANUARY 2006 – REVISED JANUARY 2016
NOTE
The power level at the part is assumed to be 4 dB less than the signal generator power
level. This accounts for 1 dB for cable losses and 3 dB for the pad.
The power level range where the frequency is correct at the Ftest/LD pin to within 1 Hz accuracy is recorded for
the sensitivity limits. The temperature, frequency, and voltage can be varied to produce a family of sensitivity
curves. Because this is an open-loop test, the charge pump is set to TRI-STATE and the unused side of the PLL
(RF or IF) is powered down when not being tested. For this part, there are actually four frequency input pins,
although there is only one frequency test pin (Ftest/LD). The conditions specific to each pin are shown in above
table.
NOTE
For the RF N counter, a fourth order fractional modulator is used in 22-bit mode with a
fraction of 2097150 / 4194301 is used. The reason for this long fraction is to test the RF N
counter and supporting fractional circuitry as completely as possible.
7.1.4 Input Impedance Measurement
Network Analyzer
Frequency
Input Pin
Device
Under
Test
Power Supply
Evaluation Board
Figure 21. Input Impedance Measurement
Figure 21 shows the test set-up used for measuring the input impedance for the LMX2486. The DC-blocking
capacitor used between the input SMA connector and the pin being measured must be changed to a 0-Ω
resistor. This procedure applies to the FinRF, FinIF, and OSCin pins. The basic test procedure is to calibrate the
network analyzer, ensure that the part is powered up, and then measure the input impedance. The network
analyzer can be calibrated by using either calibration standards or by soldering resistors directly to the evaluation
board. An open can be implemented by putting no resistor, a short can be implemented by soldering a 0-Ω
resistor as close as possible to the pin being measured, and a short can be implemented by soldering two 100-Ω
resistors in parallel as close as possible to the pin being measured. Calibration is done with the PLL removed
from the PCB. This requires the use of a clamp down fixture that may not always be generally available. If no
clamp down fixture is available, then this procedure can be done by calibrating up to the point where the DC-
blocking capacitor usually is, and then implementing port extensions with the network analyzer. The 0-Ω resistor
is added back for the actual measurement. Once the set-up is calibrated, it is necessary to ensure that the PLL is
powered up. This can be done by toggling the power-down bits (RF_PD and IF_PD) and observing that the
current consumption indeed increases when the bit is disabled. Sometimes it may be necessary to apply a signal
to the OSCin pin to program the part. If this is necessary, disconnect the signal once it is established that the
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