LMX2486_16 Datasheet, PDF (19/47 Pages) Texas Instruments – Low-Power Dual PLLatinum Frequency Synthesizers

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8 Detailed Description
LMX2486
SNAS324B – JANUARY 2006 – REVISED JANUARY 2016
8.1 Overview
The LMX2486 consists of integrated N counters, R counters, and charge pumps. The TCXO, VCO and loop filter
are supplied external to the chip.
8.2 Functional Block Diagram
FinIF
ENOSC
OSCin
OSCout
VddRF1
VddRF2
VddRF3
VddRF4
VddRF5
FinRF
FinRF*
CE
CLK
DATA
LE
1X / 2X
IF N Divider
8/9
or
16/17
Prescaler
B Counter
A Counter
IF R
Divider
RF R
Divider
RF N Divider
16/17/20/21 C Counter
32/33o/r3R6/F3N7 ^{DividBerCounter}
Prescaler
A Counter
MICROWIRE
Interface
6'
Compensation
Phase
Comp
IF
LD
RF LD
Phase
Comp
Charge
Pump
Ftest/LD
MUX
Charge
Pump
RF Fastlock
VddIF1
VddIF2
CPoutIF
Ftest/LD
CPoutRF
FLoutRF
GND
GND
GND
8.3 Feature Description
8.3.1 TCXO, Oscillator Buffer, and R Counter
The oscillator buffer must be driven single-ended by a signal source, such as a TCXO. The OSCout pin is
included to provide a buffered output of this input signal and is active when the OSC_OUT bit is set to one. The
ENOSC pin can be also pulled high to ensure that the OSCout pin is active, regardless of the status of the
registers in the LMX2486.
The R counter divides this TCXO frequency down to the comparison frequency.
8.3.2 Phase Detector
The maximum phase detector operating frequency for the IF PLL is straightforward, but it is a little more involved
for the RF PLL because it is fractional. The maximum phase detector frequency for the LMX2486 RF PLL is 50
MHz. However, this is not possible in all circumstances due to illegal divide ratios of the N counter. The crystal
reference frequency also limits the phase detector frequency, although the doubler helps with this limitation.
There are trade-offs in choosing the phase detector frequency. If this frequency is run higher, then phase noise
will be lower, but lock time may be increased due to cycle slipping and the capacitors in the loop filter may
become rather large.
8.3.3 Charge Pump
For the majority of the time, the charge pump output is high impedance, and the only current through this pin is
the TRI-STATE leakage. However, it does put out fast correction pulses that have a width that is proportional to
the phase error presented at the phase detector.
The charge pump converts the phase error presented at the phase detector into a correction current. The
magnitude of this current is theoretically constant, but the duty cycle is proportional to the phase error. For the IF
PLL, this current is not programmable, but for the RF PLL it is programmable in 16 steps. Also, the RF PLL
allows for a higher charge pump current to be used when the PLL is locking to reduce the lock time.
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