DS92LX2121_15 Datasheet, PDF (29/44 Pages) Texas Instruments – 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121, DS92LX2122
www.ti.com
SNLS330J – MAY 2010 – REVISED JANUARY 2014
Any PASS result will remain unless it is changed by a new BIST session or cleared by asserting and releasing
PDB. The default state of PASS after a PDB toggle is HIGH.
It is important to note that AT SPEED BIST will only determine if there is an issue on the link that is not related to
the clock and data recovery of the link (whose status is flagged with LOCK pin).
LVCMOS VDDIO OPTION
1.8V or 3.3V SER Inputs and DES Outputs are user configurable to provide compatibility with 1.8V and 3.3V
system interfaces.
REMOTE WAKE UP (Camera Mode)
After initial power up, the SER is in a low-power Standby mode. The DES (controlled by the host ) 'Remote
Wakeup' register allows the DES side to generate a signal across the link to remotely wakeup the SER. Once the
SER detects the wakeup signal, the SER switches from Standby mode to active mode. In active mode, the SER
locks onto PCLK input (if present), otherwise the on-chip oscillator is used as the input clock source. Note the
host controller should monitor the DES LOCK pin and confirm LOCK = H before performing any I²C
communication across the link.
For Remote Wakeup to function properly:
• The chipset needs to be configured in Camera mode: Serializer M/S = 0 and Deserializer M/S = 1
• The SER expects remote wake up by default at power on.
• Configure the control channel driver of the DES to be in remote wake up mode by setting DES register 0x26
to 0xC0.
• Perform remote wake up on SER by setting DES register 0x01 b[2] to 1.
• Return the control channel driver of the DES to the normal operation mode by setting DES register 0x26 to 0.
The SER can also be put into standby mode by programming the DES remote wake up control register 0x01 b[2]
REM_WAKEUP to 0.
POWERDOWN
The SER has a PDB input pin to ENABLE or Powerdown the device. The modes can be controlled by the host
and is used to disable the Link to save power when the remote device is not operational. An auto mode is also
available. In this mode, the PDB pin is tied High and the SER switches over to an internal oscillator when the
PCLK stops or not present. When a PCLK starts again, the SER will then lock to the valid input PCLK and
transmits the data to the DES. In powerdown mode, the high-speed driver outputs are static (HIGH).
The DES has a PDB input pin to ENABLE or Powerdown the device. This pin can be controlled by the system
and is used to disable the DES to save power. An auto mode is also available. In this mode, the PDB pin is tied
High and the DES will enter powerdown when the serial stream stops. When the serial stream starts up again,
the DES will lock to the input stream and assert the LOCK pin and output valid data. In powerdown mode, the
Data and PCLK outputs are set by the OSS_SEL control register.
POWER UP REQUIREMENTS AND PDB PIN
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5
ms then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up
and a 22 uF cap to GND to delay the PDB input signal.
SIGNAL QUALITY ENHANCERS
Des - Receiver Input Equalization (EQ)
The receiver inputs provided input equalization filter in order to compensate for loss from the media. The level of
equalization is controlled via register setting.
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