DRV3204-Q1 Datasheet, PDF (29/38 Pages) Texas Instruments – DRV3204-Q1 Three-Phase Brushless Motor Driver

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Not Recommended for New Designs
DRV3204-Q1
SLVSBT3C – MARCH 2013 – REVISED JULY 2016
FLGLATCH_EN
Status
0
Fault
1
Fault
FLTFLG
0
1
SPI Access
to FLTFLG
(1)
FAULT
H
L
Read
Write 1
to cClear
Pre-Driver⁽²⁾ Enable Disable
(1) Assertion of FAULT occurs if FLTEN = 1.
(2) Disabling of pre-driveroccurs if SDNEN = 1.
Figure 26. FLGFLG and FLGLATCH_EN
7.3.1.9 CSCFG (address 0x0A): Current Sense Configuration Register
Bit Name
Type ⁽¹⁾
7:3 RSVD
R
2:0 CSOFFSET RW
(1) R: Read W: Write
Reset
0000 0
000
Description
Reserved
Current-sense offset
000: 0.5 V
001: 1 V
010: 1.5 V
011: 2 V
100: 2.5 V
Others: 0.5 V
7.3.1.10 PDCFG (address 0x0B): Pre-Driver Configuration Register
Bit Name
Type ⁽¹⁾
7:2 RSVD
R
1:0 DEADT RW
(1) R: Read W: Write
Reset Description
0000 00 Reserved
00
Dead time (= t_dead)
00: 2 µs
01: 1.5 µs
10: 1 µs
11: 0.5 µs
The actual dead time has ±0.2 µs variation from the typical value.
7.3.1.11 DIAG (address 0x0C): Diagnosis Register
Bit Name
7:3 RSVD
2 VCCUVRST
1 WDTRST
0 CMRST
Type
R
R
R
R
Reset
0000 0
0
0
0
Description
Reserved
nRES reset source information
Bit 2 = VCCUVRST - VCC undervoltage
Bit 1 = WDTRST - watchdog timer
Bit 0 = CMRST - clock monitor
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