DRV3204-Q1 Datasheet, PDF (24/38 Pages) Texas Instruments – DRV3204-Q1 Three-Phase Brushless Motor Driver

Not Recommended for New Designs
DRV3204-Q1
SLVSBT3C – MARCH 2013 – REVISED JULY 2016
7.3 Register Maps
MSB
D14
DIN
RW[1]
RW[0]
D7
D6
DIN
Data[7]
Data[6]
Table 3. SPI Serial Input Format
D13
D12
D11
Addr[5]
Addr[4]
Addr[3]
D5
D4
D3
Data[5]
Data[4]
Data[3]
D10
Addr[2]
D2
Data[2]
DOUT
DOUT
MSB
0
D7
Data[7]
Table 4. SPI Serial Output Data Format
D14
D13
D12
D11
D10
Frame fault
0
0
0
0
D6
D5
D4
D3
D2
Data[6]
Data[5]
Data[4]
Data[3]
Data[2]
D9
Addr[1]
D1
Data[1]
D9
0
D1
Data[1]
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D8
Addr[0]
LSB
Data[0]
D8
1
LSB
Data[0]
SPI serial input and output format
RW[1:0]
: 01: write mode; 00: read mode
Addr[5:0] : Address of SPI access
Data[7:0] : Input data to write or output data to read
Frame fault : 0: No error exists in the previous SPI frame.
: 1: Error exists in the previous SPI frame.
Register
Name
Reserved
CFGUNLK
FLTCFG
Reserved
FLTEN0
FLTEN1
SDNEN0
SDNEN1
FLTFLG0
FLTFLG1
CSCFG
PDCFG
DIAG
SPARE
Reserved
Addr
(Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E-3F
b7
FLGLATCH_EN
FE_MTOC
SE_MTOC
MTOC
Table 5. SPI Register Map
b6
b5
b4
b3
RSVD
RSVD
MTOCTH
RSVD
RSVD
FE_VCCOC FE_VCCOV FE_VDDOV FE_CPOV
RSVD
SE_VCCOC SE_VCCOV SE_VDDOV SE_CPOV
RSVD
VCCOC
VCCOV
VDDOV
CPOV
RSVD
RSVD
RSVD
RSVD
SPARE
RSVD
b2
b1
b0
CFGUNLK
VCCUVTH
VBUVTH
FE_CPUV
SE_CPUV
CPUV
VCCUVRST
FE_VBOV
FE_VBUV
FE_TSD
SE_VBOV
SE_VBUV
SE_TSD
VBOV
VBUV
TSD
CSOFFSET
DEADT
WDTRST
CMRST
SEL_COMP_HYS
Reset
(Hex)
00
00
00
00
FF
01
FF
01
00
00
00
00
00
00
00
7.3.1 Register Descriptions
Access type: R = Read and W = Write.
Reserved register: Read of reserved bits return 0 and write has no effect.
7.3.1.1 CFGUNLK (address 0x01): Configuration Unlock Register
Bit Name
Type Reset Description
3:0 CFGUNLK RW
0000
DRV3204 SPI register map has lock and unlock mode, and it is in lock mode by default. MCU
can write values of the following registers in unlock mode;
● FLTCFG
● FLTEN0 and FLTEN1
● SDNEN0 and SDNEN1
● CSCFG
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