TM4C123GH6ZXR Datasheet, PDF (282/1472 Pages) Texas Instruments – Tiva Microcontroller

System Control
Register 21: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4
This register specifies the LDO output voltage while in Sleep mode. Writes to the VLDO bit field have
no effect on the LDO output voltage, regardless of what is specified for the VADJEN bit. The LDO
output voltage is fixed at the recommended factory reset value.
The table below shows the maximum system clock frequency and PIOSC frequency with respect
to the configured LDO voltage.
Operating Voltage (LDO)
1.2
0.9
Maximum System Clock Frequency
80 MHz
20 MHz
PIOSC
16 MHz
16 MHz
Note:
■ The LDO will not automatically adjust in Sleep/Deepsleep mode if a debugger has been
connected since the last power-on reset.
■ If the LDO voltage is adjusted, it will take an extra 4 us to wake up from Sleep or
Deep-Sleep mode.
LDO Sleep Power Control (LDOSPCTL)
Base 0x400F.E000
Offset 0x1B4
Type RW, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VADJEN
reserved
Type RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
VLDO
Type RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
Bit/Field
31
Name
VADJEN
Type
RW
Reset
0
Description
Voltage Adjust Enable
This bit enables the value of the VLDO field to be used to specify the
output voltage of the LDO in Sleep mode.
Value Description
0 The LDO output voltage is set to the factory default value in
Sleep mode. The value of the VLDO field does not affect the
LDO operation.
1 The LDO output value in Sleep mode is configured by the value
in the VLDO field.
30:8
reserved
RO
0x000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
282
June 12, 2014
Texas Instruments-Production Data