TM4C123GH6ZXR Datasheet, PDF (231/1472 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C123GH6ZXR Microcontroller
To provide the lowest possible Deep-Sleep power consumption as well the ability to wake the
processor from a peripheral without reconfiguring the peripheral for a change in clock, some of the
communications modules have a Clock Control register at offset 0xFC8 in the module register space.
The CS field in the Clock Control register allows the user to select the PIOSC as the clock source
for the module's baud clock. When the microcontroller enters Deep-Sleep mode, the PIOSC becomes
the source for the module clock as well, which allows the transmit and receive FIFOs to continue
operation while the part is in Deep-Sleep. Figure 5-6 on page 231 shows how the clocks are selected.
Figure 5-6. Module Clock Selection
Clock Control Register
PIOSC
1
0
Baud Clock
System Clock
Deep Sleep
1
0
Module Clock
5.2.6.4
Additional deep-sleep modes are available that lower the power consumption of the SRAM and
Flash memory. However, the lower power consumption modes have slower deep-sleep and wake-up
times, see “Dynamic Power Management” on page 231 for more information.
Dynamic Power Management
In addition to the Sleep and Deep-Sleep modes and the clock gating for the on-chip modules, there
are several additional power mode options that allow the LDO, Flash memory, and SRAM into
different levels of power savings while in Sleep or Deep-Sleep modes. Note that these features may
not be available on all devices; the System Properties (SYSPROP) register provides information
on whether a mode is supported on a given MCU. The following registers provides these capabilities:
■ LDO Sleep Power Control (LDOSPCTL): controls the LDO value in Sleep mode
■ LDO Deep-Sleep Power Control (LDODPCTL): controls the LDO value in Deep-Sleep mode
■ LDO Sleep Power Calibration (LDOSPCAL): provides factory recommendations for the LDO
value in Sleep mode
■ LDO Deep-Sleep Power Calibration (LDODPCAL): provides factory recommendations for the
LDO value in Deep-Sleep mode
■ Sleep Power Configuration (SLPPWRCFG): controls the power saving modes for Flash memory
and SRAM in Sleep mode
■ Deep-Sleep Power Configuration (DSLPPWRCFG): controls the power saving modes for Flash
memory and SRAM in Deep-Sleep mode
June 12, 2014
231
Texas Instruments-Production Data