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TM4C123GH6ZXR Datasheet, PDF (1051/1472 Pages) Texas Instruments – Tiva Microcontroller
Tiva™ TM4C123GH6ZXR Microcontroller
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (80 MHz/(2*(2+1)*3330000))-1;
TPR = 3
Write the I2CMTPR register with the value of 0x0000.0003.
8. To send the master code byte, software should place the value of the master code byte into the
I2CMSA register and write the I2CMCS register with a value of 0x13.
9. This places the I2C master peripheral in High-speed mode, and all subsequent transfers (until
STOP) are carried out at High-speed data rate using the normal I2CMCS command bits, without
setting the HS bit in the I2CMCS register.
10. The transaction is ended by setting the STOP bit in the I2CMCS register.
11. Wait until the transmission completes by polling the I2CMCS register's BUSBSY bit until it has
been cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
16.5
Register Map
Table 16-4 on page 1051 lists the I2C registers. All addresses given are relative to the I2C base address:
■ I2C 0: 0x4002.0000
■ I2C 1: 0x4002.1000
■ I2C 2: 0x4002.2000
■ I2C 3: 0x4002.3000
■ I2C 4: 0x400C.0000
■ I2C 5: 0x400C.1000
Note that the I2C module clock must be enabled before the registers can be programmed (see
page 354). There must be a delay of 3 system clocks after the I2C module clock is enabled before
any I2C module registers are accessed.
The hw_i2c.h file in the TivaWare™ Driver Library uses a base address of 0x800 for the I2C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that TivaWare™
for C Series uses an offset between 0x000 and 0x018 with the slave base address.
Table 16-4. Inter-Integrated Circuit (I2C) Interface Register Map
Offset Name
I2C Master
0x000 I2CMSA
0x004 I2CMCS
0x008 I2CMDR
0x00C I2CMTPR
0x010 I2CMIMR
0x014 I2CMRIS
Type
Reset
Description
RW
0x0000.0000 I2C Master Slave Address
RW
0x0000.0020 I2C Master Control/Status
RW
0x0000.0000 I2C Master Data
RW
0x0000.0001 I2C Master Timer Period
RW
0x0000.0000 I2C Master Interrupt Mask
RO
0x0000.0000 I2C Master Raw Interrupt Status
See
page
1053
1054
1059
1060
1061
1062
June 12, 2014
Texas Instruments-Production Data
1051