ADS8885_14 Datasheet, PDF (28/49 Pages) Texas Instruments – 18-Bit, 400-kSPS, Serial Interface, microPower, Miniature, True-Differential Input, SAR Analog-to-Digital Converter

ADS8885
SBAS568A – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
As shown in Figure 63, the device DOUT pin is driven low when DIN and CONVST are low together. A CONVST
rising edge selects daisy-chain mode, samples the analog input, and causes the device to enter a conversion
phase. In this interface option, CONVST must remain high from the start of the conversion until all data bits are
read. When started, the conversion continues regardless of the state of SCLK, however SCLK must be high at
the CONVST rising edge so that the device generates a busy indicator at the end of the conversion.
CONVST
t_conv-max
t_conv-min
1/f_sample
t_ACQ
SCLK
t_h-DI-CNV
œœ
œœ
1
2 18
19
20
21 36
37
DIN 1 =
CONVST
DOUT 1
DIN 2
DOUT 2
ADC ^Acquiring
STATE ^{Sample N}
Converting
Sample N
End-of-
Conversion
BUSY
BUSY
œœ
D17 D1
D0
œœ
œœ
D17 D1
D0
œœ
œœ
D17
D16 D1
D0
œœ
Read Sample N
ADC 2
Read Sample N
ADC 1
Acquiring Sample N+1
Figure 63. Interface Timing Diagram: For Two Devices in Daisy-Chain Mode With a Busy Indicator
At the end of conversion, every ADC in the chain loads its own conversion result into the internal, 18-bit, shift
register and also forces its DOUT pin high, thereby providing a low-to-high transition on the IRQ pin of the digital
host. All ADCs enter an acquisition phase and power-down. On every subsequent SCLK falling edge, the internal
shift register of each ADC latches the data available on its DIN pin and shifts out the next bit of data on its DOUT
pin. Therefore, the digital host receives the interrupt signal followed by the data of ADC N followed by the data of
ADC N–1, and so on (in MSB-first fashion). A total of (18 x N) + 1 SCLK falling edges are required to capture the
outputs of all N devices in the chain. Data are valid on both edges of SCLK and can be captured on either edge.
However, a digital host capturing data on the SCLK falling edge can achieve a faster reading rate (provided
t_{h_CK_DO} is acceptable). Note that the busy indicator bits of ADC 1 to ADC N–1 do not propagate to the next
device in the chain.
POWER SUPPLY
The device has two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on
AVDD; DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the
permissible range.
Decouple the AVDD and DVDD pins with GND, using individual 1-µF decoupling capacitors placed in close
proximity to the pin, as shown in Figure 64.
Analog
Supply
1 µF
REF
DVDD
AVDD
DIN
AINP
SCLK
AINN
DOUT
GND
CONVST
Digital
Supply
1 µF
Figure 64. Supply Decoupling
28
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