ADS8885_14 Datasheet, PDF (21/49 Pages) Texas Instruments – 18-Bit, 400-kSPS, Serial Interface, microPower, Miniature, True-Differential Input, SAR Analog-to-Digital Converter

ADS8885
www.ti.com
SBAS568A – MAY 2013 – REVISED DECEMBER 2013
3-Wire CS Mode Without a Busy Indicator
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host. In this
interface option, DIN can be connected to DVDD and CONVST functions as CS (as shown in Figure 50). As
shown in Figure 51, a CONVST rising edge forces DOUT to 3-state, samples the input signal, and causes the
device to enter a conversion phase. Conversion is done with the internal clock and continues regardless of the
state of CONVST. As a result, CONVST (functioning as CS) can be pulled low after the start of the conversion to
select other devices on the board. However, CONVST must return high before the minimum conversion time
(t_conv-min) elapses and is held high until the maximum possible conversion time (t_conv-max) elapses. A high level on
CONVST at the end of the conversion ensures the device does not generate a busy indicator.
DVDD
CONVST
CNV
DIN
SCLK
CLK
DOUT
SDI
ADC
Digital Host
Figure 50. Connection Diagram: 3-Wire CS Mode Without a Busy Indicator (DIN = 1)
DIN = HIGH
CONVST
CONVST = 1
1/f_sample
SCLK
œœ
1
2
3 16
17
18
DOUT
ADC Acquiring
STATE ^{Sample N}
t_conv-max
t_conv-min
Converting
Sample N
End-of-Conversion
œœ
D17
D16 D15 D2
D1
D0
œœ
t_ACQ
Conversion Result of Sample N Clocked-out
while Acquiring Sample N+1
Figure 51. Interface Timing Diagram: 3-Wire CS Mode Without a Busy Indicator (DIN = 1)
When conversion is complete, the device enters an acquisition phase and powers down. CONVST (functioning
as CS) can be brought low after the maximum conversion time (t_conv-max) elapses. On the CONVST falling edge,
DOUT comes out of 3-state and the device outputs the MSB of the data. The lower data bits are output on
subsequent SCLK falling edges. Data are valid on both SCLK edges. Data are valid on both edges of SCLK and
can be captured on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a
faster reading rate (provided t_{h_CK_DO} is acceptable). DOUT goes to 3-state after the 18th SCLK falling edge or
when CONVST goes high, whichever occurs first.
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: ADS8885
Submit Documentation Feedback
21