ADS8885_14 Datasheet, PDF (22/49 Pages) Texas Instruments – 18-Bit, 400-kSPS, Serial Interface, microPower, Miniature, True-Differential Input, SAR Analog-to-Digital Converter

ADS8885
SBAS568A – MAY 2013 – REVISED DECEMBER 2013
www.ti.com
3-Wire CS Mode With a Busy Indicator
This interface option is most useful when a single ADC is connected to an SPI-compatible digital host and an
interrupt-driven data transfer is desired. In this interface option, DIN can be connected to DVDD and CONVST
functions as CS (as shown in Figure 52). The pull-up resistor on the DOUT pin ensures that the IRQ pin of the
digital host is held high when DOUT goes to 3-state. As shown in Figure 53, a CONVST rising edge forces
DOUT to 3-state, samples the input signal, and causes the device to enter a conversion phase. Conversion is
done with the internal clock and continues regardless of the state of CONVST. As a result, CONVST (functioning
as CS) can be pulled low after the start of the conversion to select other devices on the board. However,
CONVST must be pulled low before the minimum conversion time (t_conv-min) elapses and must remain low until
the maximum possible conversion time (t_conv-max) elapses. A low level on the CONVST input at the end of a
conversion ensures the device generates a busy indicator.
DVDD
DIN
CONVST
SCLK
DVDD
CNV
CLK
DOUT
SDI
ADC
IRQ
Digital Host
Figure 52. Connection Diagram: 3-Wire CS Mode With a Busy Indicator
DIN = DVDD
1/f_sample
CONVST
CONVST = 0
SCLK
œœ
1
2
3 17
18
19
DOUT
ADC ^Acquiring
STATE ^{Sample N}
SDO Pulled-up
t_conv-min
t_conv-max
Converting
Sample N
End-of-Conversion
BUSY
œœ
D17 D16 D2
D1
D0
œœ
t_ACQ
Conversion Result of Sample N Clocked-out
while Acquiring Sample N+1
Figure 53. Interface Timing Diagram: 3-Wire CS Mode With a Busy Indicator (DIN = 1)
When conversion is complete, the device enters an acquisition phase and powers down, DOUT comes out of 3-
state, and the device outputs a busy indicator bit (low level) on the DOUT pin. This configuration provides a high-
to-low transition on the IRQ pin of the digital host. The data bits are clocked out, MSB first, on the subsequent
SCLK falling edges. Data are valid on both SCLK edges. Data are valid on both edges of SCLK and can be
captured on either edge. However, a digital host capturing data on the SCLK falling edge can achieve a faster
reading rate (provided t_{h_CK_DO} is acceptable). DOUT goes to 3-state after the 19th SCLK falling edge or when
CONVST goes high, whichever occurs first.
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