ADS7041 Datasheet, PDF (28/37 Pages) Texas Instruments – Ultra-Low Power, Ultra-Small Size, 10-Bit, 1-MSPS, SAR ADC

ADS7041
SBAS675A – NOVEMBER 2014 – REVISED NOVEMBER 2014
www.ti.com
Table 5 lists the acquisition time for the above two cases for a throughput of 100 kSPS. Clearly, case 2 provides
more acquisition time for the input signal to settle.
CASE
1
2
SCLK
1.4 MHz
14 MHz
Table 5. Acquisition Time with Different SCLK Frequencies
t_cycle
10 µs
10 µs
CONVERSION TIME
(= 10.5 × t_SCLK + t_{SU_CSCK})
7.65 µs
0.765 µs
ACQUISITION TIME
(= t_cycle – t_conv)
2.35 µs
9.235 µs
For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation
results, and test results, refer to TI Precision Design TIPD168, Three 12-Bit Data Acquisition
Reference Designs Optimized for Low Power and Ultra-Small Form Factor (TIDU390).
9.2.3.3 Application Curve
When the output impedance of the sensor increases, the time required for the input signal to settle increases and
the performance of the SAR ADC starts degrading if the input signal does not settle within the acquisition time of
the ADC. The performance of the SAR ADC can be improved by reducing the throughput to provide enough time
for the input signal to settle. Figure 46 provides the results for ENOB achieved from the ADS7041 for case 2 at
different throughputs with different input impedances at the device input.
12
11.5
11
25 and 1.5 nF
250 and1.5 nF
2.5 k and1.5 nF
10 k and1.5 nF
25 k and1.5 nF
50 k and1.5 nF
10.5
10
9.5
9
0
200
400
600
800
1000
Sampling Rate (kSPS)
C030
Figure 46. ENOB (Effective Number of Bits) Achieved from the ADS7041 at Different Throughputs
Table 6 shows the results and performance summary for this 12-Bit, 10-kSPS DAQ circuit application.
Table 6. Results and Performance Summary for 10-Bit, 10-kSPS DAQ Circuit for DC Sensor
Measurements
DESIGN PARAMETER
Throughput
SNR at 100 Hz
THD at 100 Hz
SINAD at 100 Hz
ENOB
Power
GOAL VALUE
10 kSPS
60.5 dB
70dB
60dB
9
10 µW
ACHIEVED RESULT
10 kSPS
61.3 dB
75 dB
61.1 dB
9.87
6 µW
28
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