ADS7041 Datasheet, PDF (20/37 Pages) Texas Instruments – Ultra-Low Power, Ultra-Small Size, 10-Bit, 1-MSPS, SAR ADC

ADS7041
SBAS675A – NOVEMBER 2014 – REVISED NOVEMBER 2014
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8.4.1.2 Offset Calibration During Normal Operation
Offset calibration can be done during normal device operation if at least 32 SCLK falling edges are provided in
one serial transfer frame. During the first 12 SCLKs, the device converts the sample acquired on the CS falling
edge and provides data on the SDO output. The device initiates the offset calibration on the 17th SCLK falling
edge and calibration completes on the 32nd SCLK falling edge. The SDO output remains low after the 12th
SCLK falling edge and SDO goes to tri-state after CS goes high. If the device is provided with less than 32
SCLKs during a serial transfer frame, the OCR is not updated. Table 3 provides the timing parameters for offset
calibration during normal operation.
For subsequent samples, the device adjusts the conversion results with the value stored in the OCR. The
conversion result adjusted with the value stored in the OCR is provided by the device on the SDO output.
Figure 38 shows the timing diagram for offset calibration during normal operation.
f_CLK-CAL
f_CLK-CAL
t_CAL
t_ACQ
t_{PH_CS}
t_{SU_CSCK}
t_{D_CKCS}
Table 3. Offset Calibration During Normal Operation
PARAMETER
MIN
TYP
SCLK frequency for calibration for 2.25 V < AVDD < 3.6 V
SCLK frequency for calibration for 1.8 V < AVDD < 2.25 V
Calibration time during normal operation
Acquisition time
15 t_SCLK
235
CS high time
t_ACQ
Setup time: CS falling to SCLK falling
15
Delay time: last SCLK falling to CS rising
10
Sample
N
t_CONV
CS
t_{SU_CSCK}
t_CAL
MAX
14
12
UNIT
MHz
MHz
ns
ns
ns
ns
ns
t_{PH_CS}
t_ACQ
Sample
N+1
t_{D_CKCS}
SCLK(f_CLK-CAL)
1
2
3
4
11 12
16 17 18
31 32
SDO
0
0 D9 D8
D1 D0
Data for Sample N
Figure 38. Offset Calibration During Normal Operation Timing Diagram
20
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