THS4520_14 Datasheet, PDF (27/37 Pages) Texas Instruments – WIDEBAND, LOW NOISE, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIER

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THS4520
SLOS503B – SEPTEMBER 2006 – REVISED JULY 2007
6
RL=200ohms
Vs = 3.3V
5.5
5
4.5
4
3.5
-90dBc
-80dBc -70dBc
-60dBc
-50dBc
-40dBc
3
2.5
-100dBc
2
1.5
-110dBc
1
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
log₁₀[Frequency(MHz)]
Figure 70. Constant HD2 Contours vs Output Swing and log₁₀ (Frequency - MHz)
V_s = 1.65 V, Gain = 1, R_L = 200 Ω
Layout Recommendations
It is recommended to follow the layout of the external
components near the amplifier, ground plane
construction, and power routing of the EVM as
closely as possible. General guidelines are:
1. Signal routing should be direct and as short
as possible into and out of the op amp circuit.
2. The feedback path should be short and direct
avoiding vias.
3. Ground or power planes should be removed
from directly under the amplifier’s input and
output pins.
4. An output resistor is recommended on each
output, as near to the output pin as possible.
5. Two 10-μF and two 0.1-μF power-supply
decoupling capacitors should be placed as
near to the power-supply pins as possible.
6. Two 0.1-μF capacitors should be placed
between the CM input pins and ground. This
limits noise coupled into the pins. One each
should be placed to ground near pin 4 and pin
9.
7. It is recommended to split the ground pane on
layer 2 (L2) as shown below and to use a
solid ground on layer 3 (L3). A single-point
connection should be used between each split
section on L2 and L3.
8. A single-point connection to ground on L2 is
recommended for the input termination
resistors R1 and R2. This should be applied to
the input gain resistors if termination is not
used.
9. The THS4520 recommended PCB footprint is
shown in Figure 71.
0.144
0.049
Pin 1
0.0095
0.015
0.144
0.012
0.0195 0.0705
0.032
0.010
vias
0.0245
Top View
0.030
Figure 71. QFN Etch and Via Pattern
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