SN74SSTU32866A Datasheet, PDF (27/35 Pages) Texas Instruments – 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

SN74SSTU32866A
25ĆBIT CONFIGURABLE REGISTERED BUFFER
WITH ADDRESSĆPARITY TEST
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
timing diagram for the first SN74SSTU32866A (1:2 Register-A configuration) device used in pair;
C0 = 0, C1 = 1 (RESET switches from L to H)
RESET
DCCSRS^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
CCLLKK^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
n
n+1
n+2
n+3
n+4
D1−D14†^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtaÎÎÎct}
tsu
th
tpdm, tpdmss
CLK to Q
Q1−Q14
PAR_IN†^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
tsu
PPO
QERR^‡
(not used)
tPHL
CLK to QERR
Data to QERR
Latency
ÎÎÎÎÎÎÎÎÎÎ _{H, L, or X}
th
tpd
CLK to PPO
tPHL, tPLH
CLK to QERR
H or L
† _{After RESET is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum time of tact max,}
to avoid false error.
‡ _{If the data is clocked in on the n clock pulse, then the QERR output signal will be generated on the n + 1 clock pulse, and it will be valid}
on the n + 2 clock pulse.
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