SN74SSTU32866A Datasheet, PDF (12/35 Pages) Texas Instruments – 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

SN74SSTU32866A
25ĆBIT CONFIGURABLE REGISTERED BUFFER
WITH ADDRESSĆPARITY TEST
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
TERMINAL FUNCTIONS
TERMINAL NAME
DESCRIPTION
GND
Ground
VCC
VREF
CLK
Power-supply voltage
Input reference voltage
Positive master clock input
CLK
Negative master clock input
C0, C1
Configuration control input. Register A or Register B and 1:1 mode or 1:2 mode select.
RESET
Asynchronous reset input. Resets registers and disables VREF, data, and clock
differential-input receivers. When RESET is low, all Q outputs are forced low and the QERR
output is forced high.
D1−D25
CSR, DCS
Data input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK.
Chip select inputs. Disables D1−D25† outputs switching when both inputs are high.
DODT
The outputs of this register bit will not be suspended by the DCS and CSR control
DCKE
The outputs of this register bit will not be suspended by the DCS and CSR control
PAR_IN
Q1−Q25‡
PPO
Parity input. Arrives one clock cycle after the corresponding data input.
Data outputs that are suspended by the DCS and CSR control
Partial parity out. Indicates odd parity of inputs D1−D25.†
QCS
Data output that will not be suspended by the DCS and CSR control
QODT
Data output that will not be suspended by the DCS and CSR control
QCKE
Data output that will not be suspended by the DCS and CSR control
QERR
Output error bit. Timing is determined by the device mode.
NC
No internal connection
DNU
Do not use. Inputs are in standby-equivalent mode, and outputs are driven low.
† _{Data inputs = D2, D3, D5, D6, D8−D25 when C0 = 0 and C1 = 0}
Data inputs = D2, D3, D5, D6, D8−D14 when C0 = 0 and C1 = 1
Data inputs = D1−D6, D8−D10, D12, D13 when C0 = 1 and C1 = 1.
‡ _{Data outputs = Q2, Q3, Q5, Q6, Q8−Q25 when C0 = 0 and C1 = 0}
Data outputs = Q2, Q3, Q5, Q6, Q8−Q14 when C0 = 0 and C1 = 1
Data outputs = Q1−Q6, Q8−Q10, Q12, Q13 when C0 = 1 and C1 = 1.
ELECTRICAL
CHARACTERISTICS
Ground input
1.8 V nominal
0.9 V nominal
Differential input
Differential input
LVCMOS input
LVCMOS input
SSTL_18 inputs
SSTL_18 inputs
SSTL_18 input
SSTL_18 input
SSTL_18 input
1.8 V CMOS outputs
1.8 V CMOS output
1.8 V CMOS output
1.8 V CMOS output
1.8 V CMOS output
Open-drain output
RESET
H
H
H
H
H
H
L
DCS
L
L
X
X
H
X
X or
floating
FUNCTION TABLES
INPUTS
CSR CLK CLK
X
↑
↓
X
↑
↓
L
↑
↓
L
↑
↓
H
↑
↓
X
L or H L or H
X or
X or
X or
floating floating floating
Dn
L
H
L
H
X
X
X or
floating
OUTPUTS
Qn
L
H
L
H
Q0
Q0
L
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