SN74SSTU32866A Datasheet, PDF (1/35 Pages) Texas Instruments – 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

SN74SSTU32866A
25ĆBIT CONFIGURABLE REGISTERED BUFFER
WITH ADDRESSĆPARITY TEST
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
D Member of the Texas Instruments
Widebus+ Family
D Pinout Optimizes DDR2 DIMM PCB Layout
D Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer
D Chip-Select Inputs Gate the Data Outputs
from Changing State and Minimizes System
Power Consumption
D Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
D Supports SSTL_18 Data Inputs
D Differential Clock (CLK and CLK) Inputs
D Supports LVCMOS Switching Levels on the
Control and RESET Inputs
D Checks Parity on DIMM-Independent Data
Inputs
D Able to Cascade with a Second
SN74SSTU32866A
D RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low, Except QERR
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V_CC operation. In the
1:1 pinout configuration, only 1 device per DIMM is required to drive 9 SDRAM loads. In the 1:2 pinout
configuration, 2 devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs which are LVCMOS. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the
open-drain error (QERR) output.
The SN74SSTU32866A buffer operates from a differential clock (CLK and CLK). Data are registered at the
crossing of CLK going high and CLK going low.
The SN74SSTU32866A buffer accepts a parity bit from the memory controller on the parity bit (PAR_IN) input,
compares it with the data received on the DIMM-independent D-inputs (D2−D3, D5−D6, D8−D25 when C0 = 0
and C1 = 0; D2−D3, D5−D6, D8−D14 when C0 = 0 and C1=1; or D1−D6, D8−D13 when C0 = 1 and C1 = 1)
and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is
even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs,
combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known
logic state.
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the
PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the
data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.
ORDERING INFORMATION
TA
PACKAGE^†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 70°C LFBGA − ZKE
Tape and reel SN74SSTU32866AZKER SU866A
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2005, Texas Instruments Incorporated
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