LP3941 Datasheet, PDF (27/34 Pages) Texas Instruments – Cellular Phone Power Management Unit

Note 21: If LDO1 output drops below 85% of nominal output level, LP3941A waits for 90 ms for it to recover to 93% (with RESET = ‘0’) before powering down.
If LDO1 output reaches 93%, power-up sequence resumes with 40 ms RESET delay.
Note 22: LP3941A powers down after PS_HOLD has been low for >35 ms continuously. ON-signal, HF_PWR, CHG_IN or RTC ALARM have no control over
shutdown operation, but it has to be initiated using PS_HOLD.
Power-Up/Down Reason and Status
Register Operation
Register h’0d stores the reason (the activating signal) for
powering up the PMU. The possible inputs that can activate
the LP3941 are the ON, HF_PWR, RTC ALARM and
CHG_IN signals. The signal that activated the LP3941A will
have its corresponding bit set to ‘1’. If multiple signals activate
the PMU simultaneously then they are all marked with ‘1’ in
register h’0d.
Register h’2e maintains the current status of ON, HF_PWR
and RTC_ALARM signals and indicates the presence of an
external charger connected to the PMU. This register shows
the current status of the inputs whereas h’0d indicates the
reason for power-up and remains thereafter static until an-
other power-up sequence occurs.
Register h’2e also indicates the status of the two comparator
outputs and the status of the ADC as well.
Note that the bit indicating the presence of an external charger
voltage in register h’2e differs provides different information
than that in register h’0d. Register h’0d CHG_IN-bit is ‘1’ if
CHG_IN-pin was logic high at start-up. Register h’2e Charger
Present-bit indicates whether the CHG_IN pin voltage is with-
in acceptable limits (4.5V ≤ V_{CHG_IN} ≤ 6.0V) for charging. If
the V_{CHG_IN} is valid for charging then this bit in register h’2e
is set to ‘1’.
Flowchart Operation
The power-up/power-down state machine is reset when
VBATT pin is less than 2.1V. The state machine is reset into
the POWEROFF state. In this state the UVLO in enabled. All
other functions except the RTC_LDO are off.
If an external charger or hands free power is connected, the
state machine advances to the EXTERNAL STANDBY state
and waits for the battery voltage to reach 3.0V. When the bat-
tery voltage reaches 3.0V the state machine advances to the
TURNON LDOs state. In the EXTERNAL STANDBY state
UVLO is enabled.
If the battery voltage reaches 3.0V before hands free power
or a charger is connected the state machine advances to the
STANDBY state. The back-up battery charger is enabled. If
the ON-key is pressed, a charger is inserted, hands free pow-
er is connected or the RTC_ALARM goes high the state
machine advances to the TURNON LDOs state.
Once in the TURNON LDOs state LDOs 1, 3 and 5 are en-
abled. The state machine remains in this state until LDO1
output reaches 93% of its nominal value or 60 ms have
passed. If LDO1 reaches 93%, the state machine advances
to the RESET OFF DELAY state. If 60 ms have passed before
the 93% level is achieved, the state machine returns to the
STANDBY state and waits for another wakeup source.
The RESET OFF DELAY state counts off 40 ms. If the battery
voltage drops below the UVLO threshold of 2.5V, the state
machine goes to the ENABLE RESET state and power down
sequence. If LDO1 output drops below 85% of the nominal
voltage the state machine returns to the TURNON LDOs state
in an attempt to restart the LDO. If neither of these conditions
occurs the state machine advances to the PS_HOLD DE-
TECT state.
In the PS_HOLD DETECT, RESET is deasserted and the
state machine waits 35 ms for the PS_HOLD signal to go high.
If PS_HOLD goes high within 35 ms of RESET going low the
state machine advances to the IDLE state. If PS_HOLD in still
low after 35 ms the state machine goes to ENABLE RESET
state and the power down sequence. If battery voltage pins
drops below the UVLO threshold, the state machine ad-
vances to the ENABLE RESET state and the power down
sequence. If LDO1 output drops below its 85% point the state
machine returns to the TURNON LDOs state in an attempt to
try restart the LDOs.
The state machine remains in the IDLE state until PS_HOLD
goes low for 35 ms. If PS_HOLD is low for less than 35 ms
the state machine remains in the IDLE state. If PS_HOLD
stays low for more than 35 ms, the state machine advances
to the ENABLE RESET state and the power down sequence.
If LDO1 output falls below its 85% point the state machine
returns to the TURNON LDOs state in an attempt to restart
the LDOs. The UVLO is disabled in the IDLE state. The back-
up battery charger is on.
In the ENABLE RESET state RESET is asserted. After
60 ms all LDOs are turned off. UVLO as well as the back-up
battery charger are on. Once LDO1 falls to its 85% point the
state machine returns to the STANDBY state.
The RTC_LDO is powered by the back-up battery and is al-
ways on (unless specifically disabled via the I²C interface).
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200945 Version 4 Revision 2 Print Date/Time: 2011/10/25 13:09:13