DS92LV0421_14 Datasheet, PDF (27/49 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
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PDB
L
L
H
H
H
H
INPUTS
OEN
X
X
L
H
L
H
SNLS325C – MAY 2010 – REVISED APRIL 2013
Table 5. Des Output State Table
OSS_SEL
X
L
H
H
X
X
LOCK
X
L
L
L
H
H
OUTPUTS
OTHER OUTPUTS
TxCLKOUT is TRI-STATE
TxOUT[3:0] are TRI-STATE
PASS is TRI-STATE
TxCLKOUT is TRI-STATE
TxOUT[3:0] are TRI-STATE
PASS is HIGH
TxCLKOUT is TRI-STATE
TxOUT[3:0] are TRI-STATE
PASS is TRI-STATE
TxCLKOUT is TRI-STATE or OSC Output through Register bit
TxOUT[3:0] are TRI-STATE
PASS is TRI-STATE
TxCLKOUT is TRI-STATE
TxOUT[3:0] are TRI-STATE
PASS is HIGH
TxCLKOUT is Active
TxOUT[3:0] are Active
PASS is Active
(Normal operating mode)
Des — Integrated Signal Conditioning Features — Des
Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 0.1μF capacitor may be connected to this pin to Ground.
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input.
Note this function cannot be seen at the RxIN+/- input. The equalization feature may be controlled by the
external pin or by register.
Table 6. Receiver Equalization Configuration Table
EQ (Strap Option)
L
H
Effect
OFF, ~1.625 dB
~13 dB
EMI Reduction Features
Des — VOD Select (VODSEL)
The differential output voltage of teh Channel Link interface is controlled by the VODSEL input.
Table 7. Des — Differential Output Voltage Table
VODSEL
L
H
Result
VOD is 250 mV TYP (500 mVp-p)
VOD is 400 mV TYP (800 mVp-p)
Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2% (4% total) at up
to 100 kHz modulations is available. See Table 8. This feature may be controlled by external STRAP pins or by
register.
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