DS92LV0421_14 Datasheet, PDF (21/49 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
www.ti.com
SNLS325C – MAY 2010 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
The DS92LV0421 / DS92LV0422 chipset transmits and receives 24-bits of data and 3 control signals, formatted
as Channel Link LVDS data, over a single serial CML pair operating at 280 Mbps to 2.1 Gbps serial line rate.
The serial stream contains an embedded clock, video control signals and is DC-balance to enhance signal
quality and supports AC coupling.
The Des can attain lock to a data stream without the use of a separate reference clock source, which simplifies
system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data pattern,
delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without the need
of special training patterns or sync characters. The Des recovers the clock and data by extracting the embedded
clock information, validating and then deserializing the incoming data stream providing a parallel Channel Link
LVDS bus to the display, ASIC, or FPGA.
The DS92LV0421 / DS92LV0422 chipset can operate with up to 24 bits of raw data with three slower speed
control bits encoded within the serial data stream. For applications that require less the maximum 24 pclk speed
bit spaces, the user will need to ensure that all unused bit spaces or parallel LVDS channels are set to valid logic
states, as all parallel lanes and 27 bit spaces will always be sampled.
See Block Diagrams.
Parallel LVDS Data Transfer
The DS92LV0421/DS92LV0422 can be configured to accept/transmit 24-bit data with 2 different mapping
schemes: The normal Channel Link LVDS format (MSBs on LVDS channel 3) can be selected by configuring the
MAPSEL pin to HIGH. See Figure 14 for the normal Channel Link LVDS mapping. An alternate mapping scheme
is available (LSBs on LVDS channel 3) by configuring the MAPSEL pin to LOW. See Figure 15 for the alternate
LVDS mapping. The mapping schemes can also be selected by register control.
The alternate mapping scheme is useful in some applications where the receiving system, typically a display,
requires that the LSBs for the 24-bit color data be sent on LVDS channel 3.
Serial Data Transfer
The DS92LV0421 transmits a pixel of data in the following format: C1 and C0 represent the embedded clock in
the serial stream. C1 is always HIGH and C0 is always LOW. b[23:0] contain the scrambled RGB data. DCB is
the DC-Balanced control bit. DCB is used to minimize the short and long-term DC bias on the signal lines. This
bit determines if the data is unmodified or inverted. DCA is used to validate data integrity in the embedded data
stream and can also contain encoded control (VS,HS,DE). Both DCA and DCB coding schemes are generated
by the DS92LV0421 and decoded by the paring deserializer automatically. Figure 22 illustrates the serial stream
per PCLK cycle.
C
1
C
0
Figure 22. Channel Link II Serial Stream
OPERATING MODES AND BACKWARD COMPATIBILITY (CONFIG[1:0])
The DS92LV0421 and DS92LV0422 are backward compatible with previous generations of Texas Instruments
Ser/Des. Configuration modes are provided for backwards compatibility with the DS90C241/DS90C124 and also
the DS90UR241/DS90UR124 and DS99R241/DS99R124 by setting the respective mode with the CONFIG[1:0]
pins as shown in Table 1 and Table 2. The selection also determine whether the Video Control Signal filter
feature is enabled or disabled in Normal mode. Backward compatibility modes are selectable through the control
pins only. The Control Signal Filter can be selected by pin or through register programming.
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