DS100KR800 Datasheet, PDF (27/33 Pages) Texas Instruments – Ultra Low Power, 8-Channel Repeater for Data-rates up to 10.3 Gbps

Applications Information
GENERAL RECOMMENDATIONS
The DS100KR800 is a high performance circuit capable of
delivering excellent performance. Careful attention must be
paid to the details associated with high-speed design as well
as providing a clean power supply. Refer to the information
below and Revision 4 of the LVDS Owner's Manual for more
detailed information on high speed design tips to address sig-
nal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The CML inputs and outputs have been optimized to work with
interconnects using a controlled differential impedance of 85
- 100Ω. It is preferable to route differential lines exclusively on
one layer of the board, particularly for the input traces. The
use of vias should be avoided if possible. If vias must be used,
they should be used sparingly and must be placed symmet-
rically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a
low inductance path for the return currents as well. Route the
differential signals away from other signals and noise sources
on the printed circuit board. See AN-1187 for additional infor-
mation on LLP packages.
FIGURE 5. Typical Routing Options
30148010
The graphic shown above depicts different transmission line
topologies which can be used in various combinations to
achieve the optimal system performance. Impedance discon-
tinuities at the differential via can be minimized or eliminated
by increasing the swell around each hole and providing for a
low inductance return current path. When the via structure is
associated with thick backplane PCB, further optimization
such as back drilling is often used to reduce the deterimential
high frequency effects of stubs on the signal path.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS100KR800 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the V_DD and GND planes create
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.1 μF bypass capac-
itor should be connected to each V_DD pin such that the ca-
pacitor is placed as close as possible to the DS100KR800.
Smaller body size capacitors can help facilitate proper com-
ponent placement. In the case of 3.3V mode operation with
the internal LDO regulator, recommend using capacitors with
capacitance in the range of 1.0 μF to 10 μF should be incor-
porated in the power supply bypassing design for the VIN pin.
These capacitors should be ultra-low ESR ceramic.
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