OPA314-Q1 Datasheet, PDF (26/38 Pages) Texas Instruments – 3-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS Operational Amplifier

OPA314-Q1, OPA2314-Q1, OPA4314-Q1
SLOS896B – DECEMBER 2014 – REVISED JANUARY 2017
10 Layout
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10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-
impedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to
physically separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping R_F and R_G close to the
inverting input minimizes parasitic capacitance, as shown in Figure 41.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Run the input traces
as far away from
VS+
the supply lines
as possible.
VIN
VS±
+IN
V+
GND
V±
Use a low-ESR,
ceramic bypass
capacitor.
RG
±IN
GND
OUT
Use a low-ESR,
ceramic bypass
capacitor.
VOUT
Place components
close to the device
and to each other to
reduce parasitic
errors.
RF
Copyright © 2017, Texas Instruments Incorporated
Figure 41. Operational Amplifier Board Layout for Noninverting Configuration
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