LMX2430_16 Datasheet, PDF (26/53 Pages) Texas Instruments – Dual High-Frequency Synthesizer

LMX2430, LMX2433, LMX2434
SNAS187D – FEBRUARY 2003 – REVISED JANUARY 2016
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Feature Description (continued)
9.3.8.1 Push-Pull Analog Lock-Detect Output
An analog lock-detect status generated from the phase detector is available on the Ftest/LD output pin if
selected. A push-pull configuration can be selected for the lock-detect output signal. With this configuration, the
lock-detect output goes HIGH when the charge pump is inactive. It goes LOW when the charge pump is active
during a comparison cycle. Narrow low-going pulses are observed when the charge pump turns on.
There are three separate push-pull analog lock-detect signals that are routed to the multiplexer. Two of these
monitor the lock status of the individual synthesizers. The third detects the condition when both the RF and IF
synthesizers are in a locked state. External circuitry is required to provide a steady DC signal to indicate when
the PLL is in a locked state. Refer to MUX[3:0] - Multifunction Output Select (R3[23:22]:R0[23:22]) for details on
how to program the different push-pull analog lock-detect options.
9.3.8.2 Open-Drain Analog Lock-Detect Output
The lock-detect output can be an open-drain configuration. In this configuration, the lock-detect output goes to a
high impedance state when the charge pump is inactive. It goes LOW when the charge pump is active during a
comparison cycle. When a pullup resistor is used, narrow low-going pulses are observed when the charge pump
turns on.
Similarly, three separate open-drain analog lock-detect signals are routed to the multiplexer. Two of these
monitor the lock status of the individual synthesizers. The third detects the condition when both the RF and IF
synthesizers are in a locked state. External circuitry is required to provide a steady DC signal to indicate when
the PLL is in a locked state. Refer to MUX[3:0] - Multifunction Output Select (R3[23:22]:R0[23:22]) for details on
how to program the different open-drain analog lock-detect options.
9.3.8.3 Digital Filtered Lock-Detect Output
A digital filtered lock-detect status generated from the phase detector is also available on the Ftest/LD output pin
if selected. The lock-detect digital filter compares the difference between the phases of the inputs to the PFD to
an RC-generated delay of approximately 15 ns. If the phase error is less than the 15-ns RC delay for 5
consecutive reference cycles, the PLL enters a locked state (HIGH). Once in lock, the RC delay is changed to
approximately 30 ns. Once the phase error becomes greater than the 30-ns RC delay, the PLL falls out of lock
(LOW). When the PLL is in power-down mode, the Ftest/LD output is forced LOW. A flow chart of the digital
filtered lock-detect output is shown in Figure 30.
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