ADS5263 Datasheet, PDF (26/69 Pages) Texas Instruments – Quad Channel 16-Bit, 100-MSPS High-SNR ADC 4 Vpp Full-scale Input

ADS5263
SLAS760A – MAY 2011 – REVISED AUGUST 2011
A7 - A0 D15 D14 D13 D12 D11 D10 D9 D8
IN HEX
2A
<GAIN CH4>
<GAIN CH3>
D7 D6 D5 D4
<GAIN CH2>
<GAIN Ch x> Individual channel gain control
In 16-bit ADC mode, <GAIN CH X> sets gain for channel CH X A.
In 14-bit ADC mode, <GAIN CH X> sets gain for channel CH X B.
0000
0 dB
0001
1 dB
0010
2 dB
0011
3 dB
0100
4 dB
0101
5 dB
0110
6 dB
0111
7 dB
1000
8 dB
1001
9 dB
1010
10 dB
1011
11 dB
1100
12 dB
1101 to Unused
1111
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D3 D2 D1 D0
<GAIN CH1>
A7 - A0 D15 D14 D13 D12 D11 D10 D9 D8
D7
D6
D5
D4
D3
D2
D1
D0
IN HEX
2C
0
0
0
0
0
0
0
0 <AVG OUT 4> <AVG OUT 3> <AVG OUT 2> <AVG OUT 1>
<AVG OUT 1>
00
01
10
11
<AVG OUT 2>
00
01
10
11
<AVG OUT 3>
00
These bits determine which data stream is output on LVDS pins OUT1A/1B.
(after global enable bit for averaging is enabled <EN AVG GLO> = 1)
LVDS OUT1A/1B buffers are powered down.
OUT1A/1B output digital data corresponding to the signal applied on analog input pin IN1.
OUT1A/1B output digital data corresponding to the average of signals applied on analog
input pins IN1 and IN2.
OUT1A/1B output digital data corresponding to the average of signals applied on analog
input pins IN1, IN2, IN3, and IN4.
These bits determine which data stream is output on LVDS pins OUT2A/2B
(after global enable bit for averaging is enabled <EN AVG GLO> = 1)
LVDS OUT2A/2B buffers are powered down.
OUT2A/2B output digital data corresponding to the signal applied on analog input pin IN2.
OUT2A/2B output digital data corresponding to the signal applied on analog input pin IN3.
OUT2A/2B output digital data corresponding to the average of signals applied on analog
input pins IN3 and IN4.
These bits determine which data stream is output on LVDS pins OUT3A/3B
(after global enable bit for averaging is enabled <EN AVG GLO> = 1)
LVDS OUT3A/3B buffers are powered down.
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