THS4541_16 Datasheet, PDF (25/61 Pages) Texas Instruments – THS4541 Negative Rail Input, Rail-to-Rail Output, Precision, 850-MHz Fully Differential Amplifier

www.ti.com
THS4541
SLOS375A – AUGUST 2014 – REVISED SEPTEMBER 2014
To assess closed-loop bandwidth and peaking, the noise-gain phase must be subtracted from the THS4541 Aol
phase to obtain the total phase around the loop, as shown in Figure 67.
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
10M
Aol Phase
Gain = 0.1
Gain = 1
Gain = 2
100M
Frequency (Hz)
1G
D063
Figure 67. Loop-Gain Phase for the Three Lower Gains of Figure 1
From Figure 66 and Figure 67, using Table 2, tabulate the loop-gain crossover frequency and phase margin at
these crossovers to explain the response shapes of Figure 1.
Table 2. Estimated Crossover Frequency and Phase Margin for Gains of 0.1, 1, and 2 in Figure 1
GAIN
0.1
1
2
DC NG (V/V)
1.1
1.94
2.85
0-dB LG (MHz)
457
380
302
PHASE MARGIN (°)
18
41
59
From these crossover (or 0-dB loop gain) frequencies, a good approximation for the resulting f_–3dB is to multiply
the crossover frequencies by 1.6 when the phase margin is less than 65°. Ideally, a 65° phase margin at loop-
gain crossover provides a flat Butterworth closed-loop response. The 59° phase margin for the gain of 2 setting
explains the nearly flat response for this condition with 1.6 × 302 MHz = 483 MHz, estimated with f_–3dB closely
matching the measured 500-MHz SSBW.
The very low phase margin in the attenuator setting at 0.1 V/V explains the highly peaked response in Figure 1.
This peaking can be easily compensated, as shown in the Designing Attenuators section, using feedback
capacitors and a differential capacitor across the inputs.
Considering the noise gain zero as part of the loop-gain analysis shows the importance of using relatively-low,
feedback-resistor values and minimizing layout parasitic capacitance on the input pins of the THS4541 to reduce
the effects of this feedback pole. The TINA model does a good job of predicting these issues (the model includes
the 0.85-pF differential internal capacitance); add any estimated external parasitic capacitance on the summing
junctions in simulation to predict the response shape more accurately.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: THS4541
Submit Documentation Feedback
25