THS12082_09 Datasheet, PDF (25/42 Pages) Texas Instruments – 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
timing and signal description of the THS12082 (continued)
write timing (using WR, WR-controlled)
Figure 14 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only.
The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is
the last external signal of CS0, CS1, and WR that becomes valid.
CS0
CS1
tsu(CS)
tw(WR)
th(CS)
WR
10%
10%
RD ^{ÎÎÎÎÎÎÎÎ}
ÏÏÏÏÏÏÏÏ
tsu
th
D(0–11)
90%
90%
DATA_AV ^{ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ}
Figure 14. Write Timing Diagram Using WR (WR-controlled)
write timing parameter using WR (WR-controlled)
PARAMETER
tsu(CS)
tsu
th
th(CS)
tw(WR)
Setup time, CS stable to last WR valid
Setup time, data valid to first WR invalid
Hold time, WR invalid to data invalid
Hold time, WR invalid to CS change
Pulse duration, WR active
MIN TYP MAX UNIT
0
ns
5
ns
2
ns
5
ns
10
ns
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
25