THS12082_09 Datasheet, PDF (21/42 Pages) Texas Instruments – 12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS
SLAS271B – MAY 2000 – REVISED DECEMBER 2002
timing and signal description of the THS12082
read timing (using R/W, CS0-controlled)
Figure 11 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W that becomes valid.
tw(CS)
CS0
10%
10%
90%
CS1
R/W ^{ÎÎÎÎÎÎÎÎÎ90%}
RD
D(0–11)
DATA_AV
tsu(R/W)
ta
90%
td(CSDAV)
90%
ÏÏÏÏÏÏÏÏÏ ^th(R/W)
90%
th
90%
Figure 11. Read Timing Diagram Using R/W (CS0-controlled)
read timing parameter (CS0-controlled)^†
PARAMETER
tsu(R/W)
ta
td(CSDAV)
th
th(R/W)
tw(CS)
† _{CS = CSO}
Setup time, R/W high to last CS valid
Access time, last CS valid to data valid
Delay time, last CS valid to DATA_AV inactive
Hold time, first CS invalid to data invalid
Hold time, first external CS invalid to R/W change
Pulse duration, CS active
MIN TYP MAX UNIT
0
ns
0
10 ns
12
ns
0
5 ns
5
ns
10
ns
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
21