OPA4820ID Datasheet, PDF (25/34 Pages) Texas Instruments – Quad, Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier

OPA4820
www.ti.com
d) Connections to other wideband devices on the
board may be made with short direct traces or through
onboard transmission lines. For short connections,
consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to
100mils) should be used, preferably with ground and
power planes opened up around them. Estimate the total
capacitive load and set R_S from the plot of Recommended
R_S vs Capacitive Load. Low parasitic capacitive loads
(< 5pF) may not need an R_S since the OPA4820 is
nominally compensated to operate with a 2pF parasitic
load. Higher parasitic capacitive loads without an R_S are
allowed as the signal gain increases (increasing the
unloaded phase margin). If a long trace is required, and the
6dB signal loss intrinsic to a doubly-terminated transmis-
sion line is acceptable, implement a matched impedance
transmission line using microstrip or stripline techniques
(consult an ECL design handbook for microstrip and
stripline layout techniques). A 50Ω environment is
normally not necessary onboard, and in fact, a higher
impedance environment will improve distortion as shown
in the distortion versus load plots. With a characteristic
board trace impedance defined based on board material
and trace dimensions, a matching series resistor into the
trace from the output of the OPA4820 is used as well as a
terminating shunt resistor at the input of the destination
device. Remember also that the terminating impedance
will be the parallel combination of the shunt resistor and
input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a doubly-terminated
transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as
a capacitive load in this case and set the series resistor
value as shown in the plot of R_S vs Capacitive Load. This
will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there will be some signal
attenuation due to the voltage divider formed by the series
output into the terminating impedance.
e) Socketing a high-speed part like the OPA4820 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an
extremely troublesome parasitic network, which can make
it almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the
OPA4820 onto the board.
SBOS317D − SEPTEMBER 2004 − REVISED AUGUST 2008
INPUT AND ESD PROTECTION
The OPA4820 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very small
geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device pins are
protected with internal ESD protection diodes to the power
supplies, as shown in Figure 19.
External
Pin
+V_CC
− V_CC
Figure 19. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA continuous
current. Where higher currents are possible (for example,
in systems with ±15V supply parts driving into the
OPA4820), current-limiting series resistors should be
added into the two inputs. Keep these resistor values as
low as possible since high values degrade both noise
performance and frequency response. Figure 20 shows
an example protection circuit for I/O voltages that may
exceed the supplies.
50Ω Source
174Ω
V₁
50Ω ^D1
+5V
Power−supply
decoupling not shown.
D2 ^1/4
OPA4820
50Ω
V_O
50Ω
R_G
301Ω
R_F
301Ω
−5V
D1 = D2 IN5911 (or equivalent)
Figure 20. Gain of +2 with Input Protection
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