OPA4820ID Datasheet, PDF (22/34 Pages) Texas Instruments – Quad, Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier

OPA4820
SBOS317D − SEPTEMBER 2004 − REVISED AUGUST 2008
response. Assuming a 2pF total parasitic on the inverting
node, holding R_F || R_G < 200Ω will keep this pole above
400MHz. By itself, this constraint implies that the feedback
resistor R_F can increase to several kΩ at high gains. This
is acceptable as long as the pole formed by R_F and any
parasitic capacitance appearing in parallel is kept out of
the frequency range of interest.
In the inverting configuration, an additional design
consideration must be noted. R_G becomes the input
resistor and therefore the load impedance to the driving
source. If impedance matching is desired, R_G may be set
equal to the required termination value. However, at low
inverting gains, the resulting feedback resistor value can
present a significant load to the amplifier output. For
example, an inverting gain of 2 with a 50Ω input matching
resistor (= R_G) would require a 100Ω feedback resistor,
which would contribute to output loading in parallel with the
external load. In such a case, it would be preferable to
increase both the R_F and R_G values, and then achieve the
input matching impedance with a third resistor to ground
(see Figure 2). The total input impedance becomes the
parallel combination of R_G and the additional shunt
resistor.
BANDWIDTH vs GAIN
Voltage-feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the GBP shown in the
specifications. Ideally, dividing GBP by the noninverting
signal gain (also called the noise gain, or NG) will predict
the closed-loop bandwidth. In practice, this only holds true
when the phase margin approaches 90°, as it does in
high-gain configurations. At low signal gains, most
amplifiers will exhibit a more complex response with lower
phase margin. The OPA4820 is optimized to give a
maximally-flat, 2nd-order Butterworth response in a gain
of 2. In this configuration, the OPA4820 has approximately
64° of phase margin and will show a typical −3dB
bandwidth of 240MHz. When the phase margin is 64°, the
closed-loop bandwidth is approximately √2 greater than
the value predicted by dividing GBP by the noise gain.
Increasing the gain will cause the phase margin to
approach 90° and the bandwidth to more closely approach
the predicted value of (GBP/NG). At a gain of +10, the
27MHz bandwidth shown in the Electrical Characteristics
agrees with that predicted using the simple formula and
the typical GBP of 250MHz.
OUTPUT DRIVE CAPABILITY
The OPA4820 has been optimized to drive the demanding
load of a doubly-terminated transmission line. When a 50Ω
line is driven, a series 50Ω into the cable and a terminating
50Ω load at the end of the cable are used. Under these
conditions, the cable impedance will appear resistive over
a wide frequency range, and the total effective load on the
OPA4820 is 100Ω in parallel with the resistance of the
feedback network. The electrical characteristics show a
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±3.6V swing into this load—which will then be reduced to
a ±1.8V swing at the termination resistor. The ±75mA
output drive over temperature provides adequate current
drive margin for this load. Higher voltage swings (and
lower distortion) are achievable when driving higher
impedance loads.
A single video load typically appears as a 150Ω load (using
standard 75Ω cables) to the driving amplifier. The
OPA4820 provides adequate voltage and current drive to
support up to three parallel video loads (50Ω total load) for
an NTSC signal. With only one load, the OPA4820
achieves an exceptionally low 0.01%/0.03° dG/dP error.
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. A
high-speed, high open-loop gain amplifier like the
OPA4820 can be very susceptible to decreased stability
and closed-loop response peaking when a capacitive load
is placed directly on the output pin. In simple terms, the
capacitive load reacts with the open-loop output
resistance of the amplifier to introduce an additional pole
into the loop and thereby decrease the phase margin. This
issue has become a popular topic of application notes and
articles, and several external solutions to this problem
have been suggested. When the primary considerations
are frequency response flatness, pulse response fidelity,
and/or distortion, the simplest and most effective solution
is to isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds
a zero at a higher frequency. The additional zero acts to
cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
The Typical Characteristics show the recommended R_S vs
Capacitive Load and the resulting frequency response at
the load. The criterion for setting the recommended
resistor is maximum bandwidth, flat frequency response at
the load. Since there is now a passive low-pass filter
between the output pin and the load capacitance, the
response at the output pin itself is typically somewhat
peaked, and becomes flat after the roll-off action of the RC
network. This is not a concern in most applications, but can
cause clipping if the desired signal swing at the load is very
close to the amplifier’s swing limit. Such clipping would be
most likely to occur in pulse response applications where
the frequency peaking is manifested as an overshoot in the
step response.
Parasitic capacitive loads greater than 2pF can begin to
degrade the performance of the OPA4820. Long PCB
traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to the
OPA4820 output pin (see the Board Layout section).