OPA4820ID Datasheet, PDF (24/34 Pages) Texas Instruments – Quad, Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier

OPA4820
SBOS317D − SEPTEMBER 2004 − REVISED AUGUST 2008
THERMAL ANALYSIS
The OPA4820 will not require heatsinking or airflow in
most applications. Maximum desired junction temperature
would set the maximum allowed internal power dissipation
as described below. In no case should the maximum
junction temperature be allowed to exceed +150°C.
Operating junction temperature (T_J) is given by
T_A + P_D × q_JA. The total internal power dissipation (P_D)
is the sum of quiescent power (P_DQ) and additional power
dissipated in the output stage (P_DL) to deliver load power.
Quiescent power is simply the specified no-load supply
current times the total supply voltage across the part. P_DL
will depend on the required output signal and load but
would, for a grounded resistive load, be at a maximum
when the output is fixed at a voltage equal to 1/2 of either
supply voltage (for equal bipolar supplies). Under this
worst-case condition, P_DL = V_S2/(4 × R_L), where R_L
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T_J using
all channels of an OPA4820IPW (TSSOP-14 package) in
the circuit of Figure 1 operating at the maximum specified
ambient temperature of +85°C.
P_D = 10V(25.8mA) + 4 × [5²/(4 × (100Ω || 800Ω))] = 539mW
Maximum T_J = +85°C + (539mW × 110°C/W) = 144°C
This maximum operating junction temperature is below the
absolute maximum junction temperature. Most junction
temperatures in applications will be lower since an
absolute worst-case output stage power was assumed in
this calculation.
BOARD LAYOUT
Achieving optimum performance with a high-frequency
amplifier such as the OPA4820 requires careful attention
to board layout parasitics and external component types.
Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output and inverting input pins can cause instability: on the
noninverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around
those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
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b) Minimize the distance (< 0.25”) from the power-sup-
ply pins to high-frequency 0.1µF decoupling capaci-
tors. At the device pins, the ground and power-plane
layout should not be in close proximity to the signal I/O
pins. Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power-supply connections should always
be decoupled with these capacitors. Larger (2.2µF to
6.8µF) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may
be placed somewhat farther from the device and may be
shared among several devices in the same area of the
PCB.
c) Careful selection and placement of external
components will preserve the high-frequency perfor-
mance of the OPA4820. Resistors should be a very low
reactance type. Surface-mount resistors work best and
allow a tighter overall layout. Metal-film and carbon
composition, axially leaded resistors can also provide
good high-frequency performance. Again, keep their leads
and PCB trace length as short as possible. Never use
wire-wound type resistors in a high-frequency application.
Since the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input termination resistors, should
also be placed close to the package. Where double-side
component mounting is allowed, place the feedback
resistor directly under the package on the other side of the
board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external
resistors, excessively high resistor values can create
significant time constants that can degrade performance.
Good axial metal-film or surface-mount resistors have
approximately 0.2pF in shunt with the resistor. For resistor
values > 1.5kΩ, this parasitic capacitance can add a pole
and/or a zero below 500MHz that can effect circuit
operation. Keep resistor values as low as possible
consistent with load-driving considerations. It has been
suggested here that a good starting point for design would
be to set R_G || R_F = 200Ω. Using this setting will
automatically keep the resistor noise terms low, and
minimize the effect of their parasitic capacitance.
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