OPA187_17 Datasheet, PDF (25/35 Pages) Texas Instruments – Drift, Low Power, Rail-to-Rail Output 36-V Operational Amplifiers Zero-Drift Series

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10 Layout
OPA187, OPA2187, OPA4187
SBOS807 – DECEMBER 2016
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Low-ESR, 0.1-µF ceramic bypass capacitors must be connected between each supply pin and ground; place
the capacitors as close to the device as possible. A single bypass capacitor from V+ to ground is applicable
to single-supply applications.
• To reduce parasitic coupling, run the input traces as far away from the supply lines as possible.
• A ground plane helps distribute heat and reduces EMI noise pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
VIN
RG
+
RF
VOUT
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
RG
GND
VIN
RF
N/C
±IN
+IN
V±
N/C
V+
OUT
N/C
VS+
GND
VOUT
Use low-ESR, ceramic
bypass capacitor
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
VOUT
Figure 48. Layout Example
Ground (GND) plane on another layer
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
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