DS100BR111 Datasheet, PDF (25/39 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input Equalization and Output De-Emphasis

TABLE 1. Table 10: SMBus Register Map
Address ^Register
Name
0x00
Device ID
0x01
Control 1
0x02
Control 2
0x04
Control 3
0x05
0x06
CRC 1
CRC 2
Bits
Field
Type Default
7 Reserved
R/W 0x00
6:3 I2C Address [3:0] R
2 EEPROM reading R
done
1 Reserved
RWSC
0 Reserved
RWSC
7:6 Idle Control
R/W 0x00
5:3 Reserved
R/W
2 LOS Select
R/W
1:0 Reserved
7 Reserved
6 Reserved
5 LOS override
R/W
R/W 0x00
4 LOS override
value
3 PWDN Inputs
2 PWDN Oscillator
1 Reserved
0 Reserved
7:6 eSATA Mode
R/W
Enable
5 TX_DIS Override
Enable
4 TX_DIS Value
Channel A
3 TX_DIS Value
Channel B
2 Reserved
1:0 EQ CONTROL
0x00
7:0 CRC[7:0]
R/W
7 Disable EEPROM R/W
CFG
6:5 Reserved
4 Reserved
3 CRC Slave Mode
Disable
0x00
0x10
2:1 Reserved
0 CRC Enable
EEPROM
Reg Bit
Description
set bit to 0
[6:3] SMBus strap observation
1: EEPROM Loading
0: EEPROM Done Loading
set bit to 0
set bit to 0
Yes Control
[7]: Continuous talk ENABLE (Channel A)
[6]: Continuous talk ENABLE (Channel B)
Set bits to 0
LOS Monitor Selection
1: Use LOS from CH B
0: Use LOS from CH A
Set bits to 00'b
Set bit to 0
Set bit to 0
Yes LOS pin override enable (1);
Use Normal Signal Detection (0)
Yes 1: Normal Operation
0: Output LOS
Yes 1: PWDN
Yes ^{0: Normal Operation}
Yes Set bit to 0
Yes [7] Channel A (1)
[6] Channel B (1)
1: Override Use Reg 0x04[4:3]
0: Normal Operation - uses pin
1: TX Disabled
0: TX Enabled
Set bit to 0
[1]: Channel B - EQ Stage 4 ON/OFF
[0]: Channel A - EQ Stage 4 ON/OFF
Slave Mode CRC Bits
Disable Master Mode EEPROM Configuration
Set bits to 0
Yes Set bit to 1
[1]: CRC Disable (No CRC Check)
[0]: CRC Check ENABLE
Note: With CRC check DISABLED register
updates take immediate effect on high speed
data path. With CRC check ENABLED
register updates will NOT take effect until
correct CRC value is loaded
Set bits to 0
Slave CRC Trigger
25
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