DS100BR111 Datasheet, PDF (17/39 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeater with Input Equalization and Output De-Emphasis

EEPROM Modes in DS100BR111 Devices
The DS100BR111 supports reading directly from an external
EEPROM device by implementing SMBus Master mode.
When using the SMBus master mode, the DS100 will read
directly from specific location in the external EEPROM. When
designing a system for using the external EEPROM, the user
needs to follow these specific guidelines.
• Set the DS100BR111 into SMBus Master Mode
— Float ENSMB (PIN 3)
• The external EEPROM device must support 400 KHz
operation
• The external EEPROM device address byte must be
0xA0'h
• Set the AD[3:0] inputs for SMBus address byte. When the
AD[3:0] = 0000'b, the device address byte is B0'h.
• Based on the SMBus 2.0 specification, a device can have
a 7-bit slave address of 1010 000'b. The LSB is set to 0'b
(for a WRITE). The bit mapping for SMBus is listed below:
— [7:5] = Reserved Bits from the SMBus specification
— [4:1] = Usable SMBus Address Bits
— [0] = Write Bit
• The DS100BR111 devices have AD[3:0] inputs in SMBus
mode (pins 1, 2, 9, 10). These pins set SMBus slave
address. When the AD[3:0] = 0001'b, the device address
byte is B2'h.
— [7:5] = Default to 3b'101
— [4:1] = Address of 4'b0001
— [0] = Write Bit, 1'b0
• The device address can be set with the use of the AD[3:0]
input up to 16 different addresses. Use the example below
to set each of the SMBus addresses.
— AD[3:0] = 0001'b, the device address byte is B2'h
— AD[3:0] = 0010'b, the device address byte is B4'h
— AD[3:0] = 0011'b, the device address byte is B6'h
— AD[3:0] = 0100'b, the device address byte is B8'h
• The master implementation in the DS100BR111 supports
multiple devices reading from 1 EEPROM. When tying
multiple devices to the SDA and SCL pins, use these
guidelines:
— Use adjacent SMBus addresses for the 4 devices
— Use a pull-up resistor on SDA; value = 4.7KΩ
— Use a pull-up resistor on SCL: value = 4.7KΩ
— Daisy-chain READEN# (pin 17) and DONE# (pin18)
from one device to the next device in the sequence
1. Tie READEN# of the 1st device in the chain (U1)
to GND
2. Tie DONE# of U1 to READEN# of U2
3. Tie DONE# of U2 to READEN# of U3
4. Tie DONE# of U3 to READEN# of U4
5. Optional: Tie DONE# of U4 to a LED to show each
of the devices have been loaded successfully
Master EEPROM Mode in the DS100BR111
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS100BR111 device. The first 3 bytes of the EEPROM
always contain a header common and necessary to control initialization of all devices connected to the I2C bus. CRC enable flag
to enable/disable CRC checking. There is a MAP bit to flag the presence of an address map that specifies the configuration data
start in the EEPROM. If the MAP bit is not present the configuration data start address is derived from the DS100BR111 address
and the configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM.
There are 37 bytes of data size for each DS100BR111 device.
FIGURE 6. Typical EEPROM Data Set
30138815
17
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