AM3892 Datasheet, PDF (25/270 Pages) Texas Instruments – AM389x Sitara ARM Microprocessors (MPUs)

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AM3894
AM3892
SPRS681 – OCTOBER 2010
2.9.3 TILER Extended Addressing Map
The Tiling and Isometric Lightweight Engines for Rotation (TILER) ports are mainly used for optimized 2-D
block accesses. The TILER also supports rotation of the image buffer at 0º, 90º, 180º, and 270º, with
vertical and horizontal mirroring.
The TILER includes an additional 4-GB addressing range to access the frame buffer in these rotated and
mirrored views. This range requires a thirty-third bit of address and is only accessible to peripherals that
require access to the multiple views. On the device, this is limited to the HD Video Processing Subsystem
(HDVPSS). (Other peripherals, based on ConnID, may access any one single view through the 512-MB
TILER window region located in the base 4-GB range.)
The HDVPSS may use the virtual address space of 4GB (0x1:0000:0000 – 0x1:FFFF:FFFF) since various
VPDMA clients of the HDVPSS may need to simultaneously access multiple 2-D images with different
orientations of the image buffers.
The top 4-GB address space is divided into eight sections of 512MB each. These eight sections
correspond to the eight different orientations as shown in Table 2-20.
BLOCK NAME
Tiler View 0
Tiler View 1
Tiler View 2
Tiler View 3
Tiler View 4
Tiler View 5
Tiler View 6
Tiler View 7
Table 2-20. TILER Extended Address Memory Map
START ADDRESS
(HEX)
0x1 0000 0000
0x1 2000 0000
0x1 4000 0000
0x1 6000 0000
0x1 8000 0000
0x1 A000 0000
0x1 C000 0000
0x1 E000 0000
END ADDRESS (HEX)
0x1 1FFF FFFF
0x1 3FFF FFFF
0x1 5FFF FFFF
0x1 7FFF FFFF
0x1 9FFF FFFF
0x1 BFFF FFFF
0x1 DFFF FFFF
0x1 FFFF FFFF
SIZE
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
DESCRIPTION
Natural 0° View
0° with Vertical Mirror View
0° with Horizontal Mirror View
180° View
90° with Vertical Mirror View
270° View
90° View
90° with Horizontal Mirror View
Copyright © 2010, Texas Instruments Incorporated
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