AM3892 Datasheet, PDF (133/270 Pages) Texas Instruments – AM389x Sitara ARM Microprocessors (MPUs)

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AM3894
AM3892
SPRS681 – OCTOBER 2010
100-MHz
Differential Clock
SATA SS
27-MHz
XTAL
OSC 27
DEVCLKIN
32.768-kHz
Clock
PCIe SS
Main
PLL
Clocks
432 MHz
Audio
PLL
Clocks
Video
PLL
Clocks
To USB (24 MHz)
To ARM Cortex-A8 (1 GHz)
To L3, HDVPSS (500 MHz)
To EMAC (125 MHz)
To SGX530 (333 MHz)^(A)
Audio Clock1
Audio Clock2
Audio Clock3
To RTC (32.768 kHz)
HD, SD, TMDS Clocks
DDR
PLL
Clocks
To DDR PHYs (800 MHz)
To CEC, UART, etc. (48 MHz)
To L3P, EMIF and DMM (400 MHz)
DDR Clock4 (Spare)
DDR Clock5 (Spare)
A. SGX530 is available only on the AM3894 device.
Figure 7-4. System Clocking Overview
7.3.1 Device Clock Inputs
The device has four on-chip PLLs and two reference clocks which are generated by on-chip oscillators. In
addition to the 27-MHz reference clock, a 100-MHz differential clock input is required for SATA and PCIe.
A third clock input is an optional 32.768-kHz clock input (no on-chip oscillator) for the RTC.
The device clock input (DEV_MXI/DEV_CLKIN) is used to generate the majority of the internal reference
clocks. An external square-wave clock can be supplied to DEV_CLKIN instead of using a crystal input.
The device clock should be 27 MHz.
Section 7.3.1.1 provides details on using the on-chip oscillators with external crystals for the 27-MHz
system oscillator.
7.3.1.1 Using the Internal Oscillators
When the internal oscillators are used to generate the device clock, external crystals are required to be
connected across the MXI and MXO pins, along with two load capacitors, as shown in Figure 7-5. The
external crystal load capacitors should also be connected to the associated oscillator ground pin
(DEVOSC_VSS). The capacitors should not be connected to board ground (VSS).
Copyright © 2010, Texas Instruments Incorporated
Power, Reset, Clocking, and Interrupts 133
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