AM3892 Datasheet, PDF (245/270 Pages) Texas Instruments – AM389x Sitara ARM Microprocessors (MPUs)

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AM3894
AM3892
SPRS681 – OCTOBER 2010
Table 8-76. DQS and DQ Routing Specification
NO.
PARAMETER
MIN
TYP
MAX UNIT
1 Center-to-center DQS-DQSn spacing in E0|E1|E2|E3
2w
2 DQS-DQSn skew in E0|E1|E2|E3
3 Center-to-center DQS to other DDR2 trace spacing⁽¹⁾
4 DQS/DQ nominal trace length ^(2)(3)(4)
5 DQ-to-DQS skew length mismatch^(2)(3)(4)
6 DQ-to-DQ skew length mismatch^(2)(3)(4)
7 DQ-to-DQ/DQS via count mismatch^(2)(3)(4)
8 Center-to-center DQ to other DDR2 trace spacing⁽¹⁾⁽⁵⁾
9 Center-to-center DQ to other DQ trace spacing^(1)(6)(7)
10 DQ/DQS E skew length mismatch^(2)(3)(4)
4w
DQLM-50
4w
3w
25 Mils
DQLM
DQLM+50 Mils
100 Mils
100 Mils
1 Vias
100 Mils
(1) Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(2) A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated
DQS (2 DQSs) per DDR EMIF used.
(3) A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS
(4 DQSs) per DDR EMIF used.
(4) There is no need, and it is not recommended, to skew match across data bytes; i.e., from DQS0 and data byte 0 to DQS1 and data byte
1.
(5) DQs from other DQS domains are considered other DDR2 trace.
(6) DQs from other data bytes are considered other DDR2 trace.
(7) DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.
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